公开(公告)号：US07561094B2

公开(公告)日：2009-07-14

申请号：US11889620

申请日：2007-08-15

申请人： Masao Hotta ,  Tatsuji Matsuura

发明人： Masao Hotta ,  Tatsuji Matsuura

IPC分类号： H03M1/38

CPC分类号： H03M1/0675 ,  H03M1/144 ,  H03M1/361

摘要： An analog-to-digital converter has a digital-to-analog converter, first, second and third comparators, and a sequential comparison register and control logic circuit. The digital-to-analog converter produces analog signals, the first, second and third comparators compare the input analog signal with first, second and third analog signals which are different from each other. Further, the sequential comparison register and control logic circuit controls the digital signals that are fed to the digital-to-analog converter from the first to third comparators, and outputs the digital signals as digital values obtained by subjecting the input analog signals to the analog-to-digital conversion.

摘要翻译： 模拟 - 数字转换器具有数模转换器，第一，第二和第三比较器，以及顺序比较寄存器和控制逻辑电路。 数模转换器产生模拟信号，第一，第二和第三比较器将输入模拟信号与彼此不同的第一，第二和第三模拟信号进行比较。 此外，顺序比较寄存器和控制逻辑电路控制从第一至第三比较器馈送到数模转换器的数字信号，并将数字信号作为数字值输出，该数字值通过使输入的模拟信号经受模拟 数字转换。

公开(公告)号：US20080297203A1

公开(公告)日：2008-12-04

申请号：US12189044

申请日：2008-08-08

申请人： Yoshiki Niki ,  Haruo Kobayashi ,  Koichiro Mashiko

发明人： Yoshiki Niki ,  Haruo Kobayashi ,  Koichiro Mashiko

IPC分类号： G05F3/26

CPC分类号： H03F3/45273 ,  H03F3/04 ,  H03F3/345 ,  H03F3/45183

摘要： A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.

摘要翻译： 一种电流镜电路，包括：第一电阻元件，其具有连接到第一电位的一个端子，而另一个端子连接到低于第一电位的第二电位; 运算放大器，具有连接到第一电位的高电位输入端和第一电阻元件的一个端子; 第二电阻元件，其一端连接到运算放大器的低电位输入端，而另一端连接到第二电位; 以及晶体管，其具有连接到运算放大器的输出端的第一电极，连接到运算放大器的低电位输入端和第二电阻元件的一端的第二电极和用作输出的第三电极 端子，其中第一和第二电阻元件都从具有比饱和区域更低的电压的线性区域开始操作。

公开(公告)号：US20070281415A1

公开(公告)日：2007-12-06

申请号：US11771916

申请日：2007-06-29

申请人： Kentaro Shibahara

发明人： Kentaro Shibahara

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A manufacturing method for a CMOS semiconductor device in which gate electrodes are adjusted to have different work function values comprises forming an device region of a first and second conductivity type for forming first and second MOS semiconductor element devices, respectively, in a semiconductor substrate, forming a gate insulator, forming a laminated film comprising a molybdenum film and nitrogen containing film for doping nitrogen into molybdenum, doping nitrogen from the nitrogen containing film into molybdenum, processing the laminated film into gate electrodes of the first and second MOS semiconductor element devices, removing the nitrogen containing film from the gate electrodes of the second MOS semiconductor element device and covering the gate electrode of the first MOS semiconductor element devices with a nitrogen diffusion preventing film, and reducing the nitrogen concentration in molybdenum of the gate electrodes of the second MOS semiconductor element device. Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

摘要翻译： 其中栅电极被调整为具有不同功函数的CMOS半导体器件的制造方法包括在半导体衬底中分别形成用于形成第一和第二MOS半导体元件器件的第一和第二导电类型的器件区域，形成 栅极绝缘体，形成包含钼膜和含氮氮膜的层压膜，用于将氮掺杂到钼中，将含氮膜的氮掺杂到钼中，将层压膜加工成第一和第二MOS半导体元件器件的栅电极，去除 来自第二MOS半导体元件元件的栅电极的含氮膜，并且用氮扩散防止膜覆盖第一MOS半导体元件的栅电极，并且降低第二MOS半导体的栅电极的钼中的氮浓度 元件装置。 本领域技术人员将容易想到额外的优点和修改。 因此，本发明在其更广泛的方面不限于本文所示和所述的具体细节和代表性实施例。 因此，在不脱离由所附权利要求及其等同物限定的总体发明构思的精神或范围的情况下，可以进行各种修改。

公开(公告)号：US07299394B2

公开(公告)日：2007-11-20

申请号：US10400911

申请日：2003-03-28

申请人： Ken-ichi Ichino ,  Masayuki Arai ,  Satoshi Fukumoto ,  Kazuhiko Iwasaki ,  Takeshi Shoda ,  Masayuki Sato

发明人： Ken-ichi Ichino ,  Masayuki Arai ,  Satoshi Fukumoto ,  Kazuhiko Iwasaki ,  Takeshi Shoda ,  Masayuki Sato

IPC分类号： G01R31/28

CPC分类号： G06F11/261 ,  G01R31/3172 ,  G01R31/318342 ,  G01R31/318371

摘要： The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.

摘要翻译： 本发明的目的是确定要输入到测试图案发生器的最佳初始值，以便实现集成电路的有效测试。 为了达到这个目的，通过使用任意给定的初始值执行故障模拟和反向故障模拟来获得最小测试长度; 计算可能产生比最小测试长度短的测试长度的下一个初始值，并且使用由此计算的初始值来执行故障模拟; 并且计算可能产生比该测试长度短的测试长度的下一个初始值，并且使用由此计算的初始值来执行故障模拟。 通过重复该过程，获得产生最短测试长度的初始值。

公开(公告)号：US07266578B2

公开(公告)日：2007-09-04

申请号：US10160966

申请日：2002-05-31

申请人： Naofumi Takagi

发明人： Naofumi Takagi

IPC分类号： G06F7/38

CPC分类号： G06F7/5525 ,  G06F2207/5521 ,  G06F2207/5528

摘要： A reciprocal square root for a radix of x is calculated when S[j] represents the partial result obtained after j iterations of calculation, W[j], a residual, and P[j], the product of an operand X and the S[j]. Firstly, appropriate values are set to the initial values S[0], W[0], and P[0]. Secondly, n iterations of calculations from j=0 to n−1 are performed. One calculation includes selecting a reciprocal square root digit qj+1 from the digit set {−a, . . . , −1, 0, 1, . . . , a}, and calculating a recurrence equation of the S[j], i.e., S[j+1]:=S[j]+qj+1r−j−1, a recurrence equation of the W[j], i.e., W[j+1]:=rW[j]−(2P[j]+Xqj+1r−j−1)qj+1, and a recurrence equation of the P[j], i.e., P[j+1]:=P[j]+Xqj+1r−j−1.

摘要翻译： 当S [j]表示在 j次迭代计算之后获得的部分结果时，计算 x的基数的倒数平方根W [j] ，P [j]，操作数X和S [j]的乘积。 首先，将适当的值设置为初始值S [0]，W [0]和P [0]。 其次，执行从j = 0到n-1的n次迭代计算的。 。 。 ，-1，0，1，... 。 。 ，a}，并且计算S [j]的递归方程，即S [j + 1]：= S [j] + q＆lt; j + 1＆lt; ，W [j]的递归方程，即W [j + 1]：= rW [j] - （2P [j] + Xq）j + 1 < 以及P [j]的递归方程，即P [j + 1]：= P [j] + Xq < SUB> j + 1 -j-1 。