公开(公告)号：US07441109B2

公开(公告)日：2008-10-21

申请号：US11384024

申请日：2006-03-17

申请人： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

发明人： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

IPC分类号： G06F7/38

CPC分类号： G06F11/3656 ,  G06F9/3842

摘要： A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

摘要翻译： 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。

公开(公告)号：US07240185B2

公开(公告)日：2007-07-03

申请号：US09748785

申请日：2000-12-22

申请人： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

发明人： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

IPC分类号： G06F11/36

CPC分类号： G06F11/3656

摘要： A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be “killed” later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.

摘要翻译： 计算机系统提供精确和非精确的手表模式。 计算机系统是在解码阶段确定指令的命运的流水线系统。 一旦指令被解码，它们不可能在后期被“杀死”。 根据精确的观察模式，在解码阶段保持指令，直到保护值被解析以确定该指令是否被提交。 解码单元的动作取决于当防护件已被解决时是否提交指令。 根据不精确的观察模式，指令继续被解码并正常执行，直到断点指令得到保护解决为止。 在这一点上，片上仿真器可以在转接模式下接管处理器的操作。 计算机系统可以在实现手表模式时考虑到不同的入侵级别。

公开(公告)号：US20060176748A1

公开(公告)日：2006-08-10

申请号：US11346796

申请日：2006-02-03

申请人： Francois Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

发明人： Francois Druilhe ,  Andrew Cofler ,  Denis Dutoit ,  Michel Harrand ,  Gilles Eyzat ,  Christian Freund

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

公开(公告)号：US06889313B1

公开(公告)日：2005-05-03

申请号：US09563634

申请日：2000-05-02

申请人： Andrew Cofler ,  Stéphane Bouvier ,  Laurent Wojcieszak

发明人： Andrew Cofler ,  Stéphane Bouvier ,  Laurent Wojcieszak

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3814 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885

摘要： A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.

摘要翻译： 解码单元包括分别连接以接收第一和第二预定长度的比特序列的第一和第二解码器。 第一和第二解码器并行操作以产生相应的输出。 开关根据控制实际需要解码的位序列的长度的处理器的指令模式来选择输出之一。

公开(公告)号：US06854049B2

公开(公告)日：2005-02-08

申请号：US10083629

申请日：2002-02-26

申请人： Andrew Cofler

发明人： Andrew Cofler

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3814 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3889

摘要： A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

摘要翻译： 处理单元与第一FIFO型存储器和第二FIFO型存储器相关联。 用于将存储器存储的数据加载到处理单元内的寄存器的每个指令被存储在第一FIFO型存储器中，并且其它操作指令被存储在第二FIFO型存储器中。 如果在第一FIFO型存储器中不存在用于修改与该操作指令相关联的寄存器的值的时间上的加载指令，则从第二FIFO型存储器移除涉及寄存器的操作指令。 在存在这种较早的加载指令的情况下，仅在从第一FIFO型存储器移除了加载指令之后，将操作指令从第二FIFO型存储器中移除。

公开(公告)号：US06807626B1

公开(公告)日：2004-10-19

申请号：US09563702

申请日：2000-05-02

申请人： Andrew Cofler ,  Stéphane Bouvier ,  Bruno Fel ,  Laurent Ducousso

发明人： Andrew Cofler ,  Stéphane Bouvier ,  Bruno Fel ,  Laurent Ducousso

IPC分类号： G06F944

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3853

摘要： A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.

摘要翻译： 计算机系统具有保存由程序指令序列组成的计算机程序的存储器。 程序指令的格式取决于计算机系统的指令模式。 解码器被布置为接收和解码程序指令。 微指令生成器响应来自解码器的信息，以根据与计算机系统的指令模式无关的预定微指令格式产生微指令。 计算机系统具有用于接收和执行微指令的多个并行执行单元。

公开(公告)号：US06742131B1

公开(公告)日：2004-05-25

申请号：US09562717

申请日：2000-05-02

申请人： Laurent Wojcieszak ,  Andrew Cofler

发明人： Laurent Wojcieszak ,  Andrew Cofler

IPC分类号： G06F132

CPC分类号： G06F9/30145 ,  G06F9/30156 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822

摘要： An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilized in that machine cycle.

摘要翻译： 描述了具有电源保护机制的指令预取缓冲器。 指令供给机构的一组输出装置各自具有停止开关，该停止开关通过改变的位序列或先前提供的位序列。 如果提供先前提供的位序列，则在该机器周期中不使用电源。

公开(公告)号：US06725365B1

公开(公告)日：2004-04-20

申请号：US09562551

申请日：2000-05-02

申请人： Andrew Cofler ,  Stéphane Bouvier

发明人： Andrew Cofler ,  Stéphane Bouvier

IPC分类号： G06F900

CPC分类号： G06F9/3804 ,  G06F9/30072

摘要： A computer system for executing instructions predicated on guard indicators included in the instructions. The instructions include normal instructions, which are executed if the guard indicator is true and branch instructions, which are executed if the guard indicator is false. The computer system is operable in a branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match. The computer system is also operable to disable the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator.

摘要翻译： 一种用于根据指令中包含的保护指示执行指令的计算机系统。 指令包括正常指令，如果保护指示灯为真，则执行，如果保护指示灯为假，则执行指令。 计算机系统可以在分支阴影模式下操作，用于将分支指令的保护指示符与随后指令中包括的保护指示器进行比较，并且如果保护指示符匹配并且用于如果保护指示符不匹配则继续提供指令 比赛。 计算机系统还可操作以在已经确定分支指令以通过解决保护指示符的状态使分支被采取而禁用分支影模式。

公开(公告)号：US5596285A

公开(公告)日：1997-01-21

申请号：US293190

申请日：1994-08-19

申请人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

发明人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

IPC分类号： H03K19/0175 ,  H03H11/30 ,  H03K19/00 ,  H04L25/08 ,  H03K17/16

CPC分类号： H03H11/30 ,  H03K19/0005 ,  H04L25/08

摘要： An integrated circuit (IC) includes a device (10) that adapts the impedance to the characteristic impedance (Zc) of transmission lines (13) each connecting a transmitter (11) to a receiver (12). Two adaptation blocks (14, 15) reproduce the respective structures of the transmitters (11) and receivers (12) and their impedance is adapted by a reference resistor (Rr). A closed loop control device (Len, Lep, Lrn, Lrp) reproduces the adaptation conditions in the transmitters (11) and receivers (12) respectively.

摘要翻译： 集成电路（IC）包括将阻抗适配到每个将发送器（11）连接到接收器（12）的传输线（13）的特性阻抗（Zc）的装置（10）。 两个适配块（14,15）再现发射器（11）和接收器（12）的相应结构，并且它们的阻抗由参考电阻器（Rr）适配。 闭环控制装置（Len，Lep，Lrn，Lrp）分别再现发射机（11）和接收机（12）中的适应条件。