Abstract:
The present application relates to apoptotic anti-IgE antibodies, nucleic acid encoding the same, therapeutic compositions thereof, and their use in the treatment of IgE-mediated disorders.
Abstract:
An integrated circuit, among other embodiments, includes an output circuit to provide a differential signal on first and second contacts during a first mode of operation, such as in a read or write mode of operation, and a single-ended signal on the first contact during a second mode of operation, such as a test mode of operation. A first variable resistor, responsive to a first control signal, is coupled to a first voltage source and the first contact. A second variable resistor, responsive to a second control signal, is coupled to a second voltage source and the second contact. A first transistor has a first electrode coupled to the first contact, a second electrode coupled to the current source and a gate to receive a first input signal. A second transistor has a first electrode coupled to the second contact, a second electrode coupled to the current source and a gate to receive a second input signal.
Abstract:
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
Abstract:
An electronic banking toy is provided. The toy may include a housing defining a storage compartment with an adjoining slot for depositing coins. A controller may display graphical and auditory representations of activities on a display screen based on the sensed location of an icon moveably mounted in a track.
Abstract:
An electronic banking toy is provided. The toy may include a housing defining a storage compartment with an adjoining slot for depositing coins. A controller may display graphical and auditory representations of activities on a display screen based on the sensed location of an icon moveably mounted in a track.
Abstract:
The present disclosure provides for electronic playsets and components thereof. An electronic playset of the present disclosure may include a see-through monitor having a transparent screen configured to display an animated image superimposed over one or more regions. The see-through monitor may be moveable by rotation or translation between one or more positions, the one or more positions being adjacent to the one or more regions. Some embodiments including a see-through monitor with a light source configured to illuminate the one or more regions. Another aspect of the present disclosure provides for a removable toy having an identifiable accessory that may be provided to an electronic playset. The playset may be configured to identify the toy and display an animated character based on the identity.
Abstract:
An interface for accessing data from one or more information systems using a wireless telephone or other user device. The interface is presented to a user as an abstraction of a unified mailbox and permits access by the user to messaging and other services from the wireless device. The interface is coupled to one or more converting modules to convert user inputs from the format in which they are received into a format that may be input to the desired information system.
Abstract:
An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
Abstract:
A wireless game controller communicates with a corresponding wireless receiver attached to a video game console. The wireless game controller accommodates a headset such that game control signals and audio signals between the wireless controller and the wireless receiver are integrated and transmitted on a single Bluetooth wireless data link.