公开(公告)号：US20070115043A1

公开(公告)日：2007-05-24

申请号：US11625711

申请日：2007-01-22

申请人： Billy Garrett ,  John Dillon ,  Michael Ching ,  William Stonecypher ,  Andy Chan ,  Matthew Griffin ,  Nancy Dillon

发明人： Billy Garrett ,  John Dillon ,  Michael Ching ,  William Stonecypher ,  Andy Chan ,  Matthew Griffin ,  Nancy Dillon

IPC分类号： G05F1/10

CPC分类号： H04L25/028 ,  G06F13/4077 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H03K19/00384 ,  H03K19/018585 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0298

摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

摘要翻译： 使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。 该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器 （输出驱动器A107和输出驱动器B111）。

公开(公告)号：US20050040878A1

公开(公告)日：2005-02-24

申请号：US10890972

申请日：2004-07-14

申请人： Billy Garrett ,  John Dillon ,  Nancy Dillon ,  Michael Ching ,  William Stonecypher ,  Andy Chan ,  Matthew Griffin

发明人： Billy Garrett ,  John Dillon ,  Nancy Dillon ,  Michael Ching ,  William Stonecypher ,  Andy Chan ,  Matthew Griffin

IPC分类号： G06F13/40 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H03L5/00

CPC分类号： H04L25/028 ,  G06F13/4077 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H03K19/00384 ,  H03K19/018585 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0298

摘要： A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.

摘要翻译： 一种操作包括输出驱动器的集成电路的方法。 该方法包括将值存储在寄存器中，其中该值表示输出驱动器的电压摆幅设置。 输出驱动器的电压摆幅设置使用保持表示电压摆幅设置的更新的计数值的计数器进行调整。 根据指示对电压摆幅设定的调整的信号来更新计数值。 此外，提供了包括输出驱动器，寄存器和计数器的集成电路存储器件。 计数器响应于指示调整计数值的方向的信号来更新计数值。

公开(公告)号：US20050099218A1

公开(公告)日：2005-05-12

申请号：US11011077

申请日：2004-12-14

申请人： Billy Garrett ,  John Dillon ,  Nancy Dillon ,  Michael Ching ,  William Stonecynher ,  Andy Chan ,  Matthew Griffin

发明人： Billy Garrett ,  John Dillon ,  Nancy Dillon ,  Michael Ching ,  William Stonecynher ,  Andy Chan ,  Matthew Griffin

IPC分类号： G06F13/40 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H03B1/00

CPC分类号： H04L25/028 ,  G06F13/4077 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H03K19/00384 ,  H03K19/018585 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0298

摘要： A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.

摘要翻译： 一种包括集成电路存储器件的系统。 集成电路装置包括用于存储代表输出电压设置的值的寄存器。 电路保持表示对输出电压设置的调整的值。 输出驱动器在校准操作期间输出驱动电压，其中基于从驱动电压导出的信号与参考电压之间的比较产生信号。 信号将表示调整的值更新为输出电压设置。

公开(公告)号：US20050083104A1

公开(公告)日：2005-04-21

申请号：US10981808

申请日：2004-11-05

申请人： Billy Garrett ,  John Dillon ,  Michael Ching ,  William Stonecynther ,  Andy Chan ,  Matthew Griffin ,  Nancy Dillon

发明人： Billy Garrett ,  John Dillon ,  Michael Ching ,  William Stonecynther ,  Andy Chan ,  Matthew Griffin ,  Nancy Dillon

IPC分类号： G06F13/40 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H03B1/00

CPC分类号： H04L25/028 ,  G06F13/4077 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H03K19/00384 ,  H03K19/018585 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0298

摘要： A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.

公开(公告)号：US20060022724A1

公开(公告)日：2006-02-02

申请号：US11237276

申请日：2005-09-27

申请人： Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

发明人： Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

IPC分类号： H03L7/00

CPC分类号： G06F1/12 ,  G06F13/423 ,  H03L7/085 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0054 ,  H04L7/02 ,  H04L7/0337

摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

公开(公告)号：US20160063109A1

公开(公告)日：2016-03-03

申请号：US14472985

申请日：2014-08-29

申请人： Yuanjie Liu ,  David Goldberg ,  Michael Ching ,  Xiaoyuan Wu ,  Joseph Anthony Beynon ,  Song Feng

发明人： Yuanjie Liu ,  David Goldberg ,  Michael Ching ,  Xiaoyuan Wu ,  Joseph Anthony Beynon ,  Song Feng

IPC分类号： G06F17/30

CPC分类号： G06F16/9535

摘要： Systems and techniques for a query-breadth selected search result sorting mechanism are herein described. A search query can be received from a user. A breadth score can be generated for the search query. A sorting mechanism can be selected from a plurality of sorting mechanisms based on the breadth score. Search results can be identified for the query and the selected sorting mechanism can be applied to the search results to produce an ordered set of search results. The ordered set of search results can be presented to the user.

摘要翻译： 这里描述了用于查询宽度选择的搜索结果分类机制的系统和技术。 可以从用户接收到搜索查询。 可以为搜索查询生成广度分数。 可以基于宽度得分从多个分选机构中选择排序机制。 可以为查询识别搜索结果，并且可以将所选择的排序机制应用于搜索结果以产生有序的搜索结果集。 搜索结果的有序集可以呈现给用户。

公开(公告)号：US07966337B2

公开(公告)日：2011-06-21

申请号：US12143885

申请日：2008-06-23

申请人： David L. Blackman ,  Michael Ching ,  Stephen Dill ,  Ivan Eduardo Gonzalez ,  Adam Marcus ,  Daniel Norin Meredith ,  Linda Anh Linh Nguyen

发明人： David L. Blackman ,  Michael Ching ,  Stephen Dill ,  Ivan Eduardo Gonzalez ,  Adam Marcus ,  Daniel Norin Meredith ,  Linda Anh Linh Nguyen

IPC分类号： G06F17/30

CPC分类号： G06F17/30864 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936

摘要： A system and method for prioritizing a fetch order of web pages. The method comprises extracting by a web crawler a set of candidate web pages to be crawled. Each web page in the set of candidate web pages is associated with a website in a computer network. A determination is made to determine if a first website score for the website is in a website score database. The first website score is associated with web pages in the set of candidate web pages if the first website score exists in the website score database. The set of candidate web pages is prioritized with respect to an associated website score for each web page in the candidate set of web pages. Content is retrieved from the set of candidate web. Hyperlinks are extracted from the content. The hyperlinks are stored in a memory unit.

摘要翻译： 用于优先处理网页的获取顺序的系统和方法。 该方法包括由网络爬行器提取要爬网的一组候选网页。 候选网页集合中的每个网页与计算机网络中的网站相关联。 确定确定网站的第一网站得分是否在网站得分数据库中。 如果网站得分数据库中存在第一个网站分数，则第一个网站得分与该候选网页集中的网页相关联。 候选网页的集合对于候选网页集合中的每个网页的相关网站评分是优先的。 从候选网络集中检索内容。 从内容中提取超链接。 超链接存储在存储单元中。

公开(公告)号：US20060067146A1

公开(公告)日：2006-03-30

申请号：US10954941

申请日：2004-09-30

申请人： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

发明人： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。 集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。 在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。 在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器 。 在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。 在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

公开(公告)号：US08149874B2

公开(公告)日：2012-04-03

申请号：US13110217

申请日：2011-05-18

申请人： Michael Ching ,  Steven Woo

发明人： Michael Ching ,  Steven Woo

IPC分类号： H04J3/16

CPC分类号： G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

摘要翻译： 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US08073009B2

公开(公告)日：2011-12-06

申请号：US12177747

申请日：2008-07-22

申请人： Michael Ching ,  Steven Woo

发明人： Michael Ching ,  Steven Woo

IPC分类号： H04J3/16

CPC分类号： G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

摘要翻译： 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。