公开(公告)号：US08043914B2

公开(公告)日：2011-10-25

申请号：US12629920

申请日：2009-12-03

Applicant: Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

Inventor： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/11524

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

Abstract translation: 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US20110256708A1

公开(公告)日：2011-10-20

申请号：US13085631

申请日：2011-04-13

Applicant: Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

Inventor： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC: H01L21/321 ,  H01L21/283

CPC classification number: H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

Abstract: A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

Abstract translation: 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US20070262075A1

公开(公告)日：2007-11-15

申请号：US11573268

申请日：2005-08-04

Applicant: Bo-Young Lee ,  Duck-Hee Ryu

Inventor： Bo-Young Lee ,  Duck-Hee Ryu

IPC: B29C65/18

CPC classification number: B29C65/20 ,  B29C57/00 ,  B29C65/30 ,  B29C66/1142 ,  B29C66/1162 ,  B29C66/5221 ,  B29C66/72523 ,  B29C66/80 ,  B29C66/8167 ,  B29C66/8414 ,  B29C66/91212 ,  B29C66/91231 ,  B29C66/91421 ,  B29C66/961 ,  B29C67/0044 ,  B29L2024/006 ,  F16L47/02

Abstract: Disclosed herein is a device and method, preventing water from leaking to the outside of a multiple wall pipe, or a hollow part in a pipe wall, and forcibly correcting differences in inside and outside diameters between pipes provided on opposite ends of a joint, and simultaneously correcting circularity of the pipe. The heat plate includes a disc, a circular groove provided on an outer surface of a side of the disc and having a V-shaped cross-section with a flat bottom, and a heat source inserted in the disc. A method of joining a multiple wall pipe includes inserting an end of the cut multiple wall pipe into a V-shaped groove of the heat plate, heating and fusing the end of the cut multiple wall pipe by applying electricity to the heat plate, and compressing and cooling the cut multiple wall pipe after the heat plate is removed.

Abstract translation: 这里公开了一种防止水泄漏到管壁内的多壁管或中空部的外部的装置和方法，并且强制地校正设置在接头的相对端的管之间的内外径的差异，以及 同时校正管道的圆度。 加热板包括盘，设置在盘的侧面的外表面上的圆形槽，具有平坦底部的V形横截面和插入盘中的热源。 连接多壁管的方法包括将切割的多壁管的一端插入加热板的V形槽中，通过向加热板施加电力来加热和熔合切割的多壁管的端部，并压缩 并且在除去加热板之后冷却切割的多壁管。

公开(公告)号：US20150064885A1

公开(公告)日：2015-03-05

申请号：US14309018

申请日：2014-06-19

Applicant: Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

Inventor： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

Abstract translation: 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

公开(公告)号：USD708207S1

公开(公告)日：2014-07-01

申请号：US29421485

申请日：2012-07-31

Applicant: Chang-Mo Yang ,  Kyung-Dae Park ,  Hye-Bin Park ,  Bo-Young Lee

Designer： Chang-Mo Yang ,  Kyung-Dae Park ,  Hye-Bin Park ,  Bo-Young Lee

公开(公告)号：US20100281585A1

公开(公告)日：2010-11-04

申请号：US12744008

申请日：2007-11-23

Applicant: Choong Min Ryu ,  Bo Young Lee ,  Soo Hyun Lee

Inventor： Choong Min Ryu ,  Bo Young Lee ,  Soo Hyun Lee

IPC: A01H5/00 ,  C07H21/02 ,  A61K31/7088

CPC classification number: A01N63/02

Abstract: The present invention relates to a composition for increasing resistance to plant pathogen by inducing an immune reaction of a plant wherein said composition comprises bacterial genetic materials as an effective component, a method for increasing resistance to plant pathogen by inducing an immune reaction of a plant wherein said method comprises a step of treating the plant with bacterial genetic materials, a plant produced by mentioned method to have increased resistance to plant pathogen, and seeds of such plant.

Abstract translation: 本发明涉及通过诱导植物的免疫反应来增加对植物病原体的抗性的组合物，其中所述组合物包含细菌遗传物质作为有效成分，通过诱导植物的免疫反应增加对植物病原体的抗性的方法，其中 所述方法包括用细菌遗传物质处理植物的步骤，通过所述方法产生的植物对植物病原体具有增加的抗性，以及这种植物的种子。

公开(公告)号：US07559251B2

公开(公告)日：2009-07-14

申请号：US11625706

申请日：2007-01-22

Applicant: Bo-Young Lee ,  Duck Hee Ryu ,  Jae Seong Kim ,  Yong Kim ,  Dae Hwan An

Inventor： Bo-Young Lee ,  Duck Hee Ryu ,  Jae Seong Kim ,  Yong Kim ,  Dae Hwan An

IPC: G01N3/32

CPC classification number: G01N3/60 ,  G01N2203/0066 ,  G01N2203/0073 ,  G01N2203/027

Abstract: Disclosed is an apparatus and method for forming thermal fatigue cracks in a test piece for performance demonstration of nondestructive testing. The apparatus for forming thermal fatigue cracks includes a heating unit, having a conductive member attached around the outer surface of a pipe test piece and an induction heating coil disposed adjacent to the conductive member; a cooling unit, having a cooling water pump for forcibly supplying cooling water to the inner surface of the pipe test piece from a cooling water storage source and a cooling water hose; and a control unit for controlling operation of the heating unit and the cooling unit. Accordingly, thermal fatigue cracks similar to actual thermal fatigue cracks occurring during the operation of nuclear power plants or processing industry equipment are formed in a test piece, thereby assuring effective performance demonstration of nondestructive testing.

Abstract translation: 公开了一种用于在无损检测的性能演示中形成试验片中的热疲劳裂纹的装置和方法。 用于形成热疲劳裂纹的装置包括加热单元，其具有附接在管道试件的外表面上的导电构件和邻近导电构件设置的感应加热线圈; 冷却单元，具有冷却水泵，用于从冷却水存储源和冷却水软管向管道试件的内表面强制供给冷却水; 以及用于控制加热单元和冷却单元的操作的控制单元。 因此，在试验片中形成类似于在核电厂或加工工业设备运行期间发生的实际热疲劳裂纹的热疲劳裂纹，从而确保了非破坏性试验的有效性能演示。

公开(公告)号：US08883611B2

公开(公告)日：2014-11-11

申请号：US13599844

申请日：2012-08-30

Applicant: Bo-Young Lee ,  Jongwan Choi ,  Myoungbum Lee

Inventor： Bo-Young Lee ,  Jongwan Choi ,  Myoungbum Lee

IPC: H01L21/76 ,  H01L27/115 ,  H01L21/764 ,  H01L21/762

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

Abstract translation: 半导体器件及其制造方法包括在彼此相邻的衬底上的多个图案之间形成沟槽，在沟槽中形成第一牺牲层，形成具有多个孔的第一多孔绝缘层 所述多个图案和所述第一牺牲层上，并且通过所述第一多孔绝缘层的所述多个孔去除所述第一牺牲层，以在所述多个图案之间和所述第一多孔绝缘层下方形成第一气隙。

公开(公告)号：US20130059422A1

公开(公告)日：2013-03-07

申请号：US13599844

申请日：2012-08-30

Applicant: Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

Inventor： Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

IPC: H01L21/764 ,  H01L21/336

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

公开(公告)号：US20120061763A1

公开(公告)日：2012-03-15

申请号：US13224427

申请日：2011-09-02

Applicant: Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

Inventor： Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L21/764 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Abstract translation: 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。