公开(公告)号：US07030707B2

公开(公告)日：2006-04-18

申请号：US10859622

申请日：2004-06-03

Applicant: Byeong-hoon Lee ,  Sun-kwon Kim

Inventor： Byeong-hoon Lee ,  Sun-kwon Kim

IPC: H03B5/24 ,  H03K3/027 ,  H03L1/00

CPC classification number: H03K3/0231 ,  G06F1/08 ,  G11C16/30

Abstract: An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.

Abstract translation: 振荡器包括比较电压产生电路，比较电路和时钟切换电路。 比较电压产生电路由电源电压驱动，并产生响应于具有与电源电压和第一参考电压成反比变化的频率的时钟信号而变化的比较电压。 比较电路将比较电压的电平与第二参考电压进行比较，并输出具有作为比较结果的逻辑电平的逻辑信号。 时钟切换电路响应于逻辑信号输出具有与电源电压成反比变化的频率的时钟信号。

公开(公告)号：US20060049621A1

公开(公告)日：2006-03-09

申请号：US11036995

申请日：2005-01-19

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/19

CPC classification number: B62D1/195

Abstract: A steering column having a variable impact-absorbing structure includes an inner column tube, an outer column tube disposed at an outer circumferential part of the inner column tube, a guide fixed to an outer circumferential surface of the outer column tube, a strap having a deformable part fitted into the guide, a pin inserted through the strap and configured to be slidable into the guide, a solenoid that drives the pin, and a control unit that controls the solenoid. The steering column further includes a sensor that senses a state of a driver and outputs the sensing result to the control unit, wherein the strap comprises a plurality of parallel wires, one end of each wire being opened and the other end of each wire being connected to each other in a closed state, and a suspending end that is bent in a loop shape is formed on the closed end to enable the inner column tube to be suspended thereon.

Abstract translation: 具有可变冲击吸收结构的转向柱包括内柱管，设置在内柱管的外周部的外柱管，固定到外柱管的外周面的引导件，具有 可变形部分装配到引导件中，插入穿过带并被构造成可滑动到引导件中的销，驱动销的螺线管和控制螺线管的控制单元。 转向柱还包括感测驾驶员的状态并将感测结果输出到控制单元的传感器，其中，所述带包括多条平行的线，每条线的一端被打开，并且每条线的另一端被连接 并且在封闭端形成弯曲成环状的悬挂端，使内筒管悬挂在其上。

公开(公告)号：US20050007201A1

公开(公告)日：2005-01-13

申请号：US10859622

申请日：2004-06-03

Applicant: Byeong-hoon Lee ,  Sun-kwon Kim

Inventor： Byeong-hoon Lee ,  Sun-kwon Kim

IPC: H03K3/354 ,  G06F1/08 ,  G11C16/30 ,  H03K3/0231 ,  H03L7/00

CPC classification number: H03K3/0231 ,  G06F1/08 ,  G11C16/30

Abstract: An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.

Abstract translation: 振荡器包括比较电压产生电路，比较电路和时钟切换电路。 比较电压产生电路由电源电压驱动，并产生响应于具有与电源电压和第一参考电压成反比变化的频率的时钟信号而变化的比较电压。 比较电路将比较电压的电平与第二参考电压进行比较，并输出具有作为比较结果的逻辑电平的逻辑信号。 时钟切换电路响应于逻辑信号输出具有与电源电压成反比变化的频率的时钟信号。

公开(公告)号：US06828848B2

公开(公告)日：2004-12-07

申请号：US10424313

申请日：2003-04-28

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: H03K301

CPC classification number: G06F1/324 ,  G05F1/465 ,  G06F1/3203 ,  H03K3/012 ,  H03K3/0315 ,  Y02D10/126

Abstract: Circuits and methods for optimizing operating performance of an integrated circuit device within a maximum allowed current by varying a period of a clock signal based on an amount of current consumed by the integrated circuit device. In one aspect, an integrated circuit device includes a plurality of functional blocks, a power supply line which supplies an internal power supply voltage to the functional blocks, a voltage converter circuit which controls an amount of current supplied to the power supply line by comparing a reference voltage with the internal power supply voltage, and a clock generator circuit which generates a clock signal that is applied to the functional blocks. The clock generator circuit adjusts a period of the clock signal according to the amount of current supplied to the power supply line.

公开(公告)号：US5638704A

公开(公告)日：1997-06-17

申请号：US555099

申请日：1995-11-08

Applicant: Jung Ho Kim ,  Hae Yoong Chung ,  Hyung Sup Kim ,  Byeong Hoon Lee ,  Young Hoon Roh

Inventor： Jung Ho Kim ,  Hae Yoong Chung ,  Hyung Sup Kim ,  Byeong Hoon Lee ,  Young Hoon Roh

IPC: D06F15/00 ,  D06F13/02 ,  D06F17/10 ,  D06F23/04 ,  D06F13/04

CPC classification number: D06F23/04 ,  D06F13/02 ,  Y10T74/18312

Abstract: A pulsator with an improved structure having a punching function is used in a washing machine. The pulsator of the present invention is composed such that a rotating member has a guiding dimple formed on its upper end surface, and an elevating member has a guiding protrusion projected from the inner surface. According to this pulsator, non-symmetrical water flow and up-and-down water flow can be generated easily so that the entanglement of the washing articles can be minimized, and the washing is carried out effectively.

Abstract translation: 具有冲孔功能的具有改进结构的波轮在洗衣机中使用。 本发明的脉动器构成为，旋转部件具有在其上端面形成的引导凹部，升降部件具有从内表面突出的引导突起。 根据该脉动器，可以容易地产生非对称的水流和上下水流，使得洗涤物品的缠结能够最小化，并且有效地进行洗涤。

公开(公告)号：US20170026088A1

公开(公告)日：2017-01-26

申请号：US14803590

申请日：2015-07-20

Applicant: JONG-PIL CHO ,  IL-JONG SONG ,  BYEONG-HOON LEE

Inventor： JONG-PIL CHO ,  IL-JONG SONG ,  BYEONG-HOON LEE

IPC: H04B5/00

CPC classification number: H04B5/0062 ,  H04B5/0031

Abstract: A method of operating a near field communication (NFC) device includes receiving, by the NFC device, a first signal from an NFC reader, transmitting, by the NFC device, a response to the first signal to the NFC reader and changing selectively, by the NFC device, a radio frequency (RF) configuration parameter associated with signal transmission operation during a signal transmission interval, based on determining whether the NFC reader recognizes the response.

Abstract translation: 操作近场通信（NFC）设备的方法包括：由NFC设备接收来自NFC读取器的第一信号，由NFC设备向NFC读取器发送对第一信号的响应，并且通过 NFC设备，基于确定NFC阅读器是否识别响应，在信号传输间隔期间与信号传输操作相关联的射频（RF）配置参数。

公开(公告)号：US08659394B2

公开(公告)日：2014-02-25

申请号：US13093254

申请日：2011-04-25

Applicant: Il-jong Song ,  Byeong-hoon Lee ,  Seung-won Lee ,  Chul-joon Choi

Inventor： Il-jong Song ,  Byeong-hoon Lee ,  Seung-won Lee ,  Chul-joon Choi

IPC: H04Q5/22 ,  H04L5/12 ,  H03D3/02

CPC classification number: G06K19/07771 ,  H04Q2213/095

Abstract: Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal.

Abstract translation: 提供了具有信号接收方法的射频识别（RFID）标签。 RFID标签包括接收包含读取数据的读取信号的解调器。 解调器包括： 电压产生电路，其提供从所接收的读取信号导出的第一电压信号和第二电压信号;反相器，其通过使用相对于所述读取信号定义的反相电压来反转所述第二电压信号来提供指示所述读取数据的数据脉冲信号 第一电压信号和通过缓冲数据脉冲信号来恢复读取数据的缓冲器。

公开(公告)号：US20110101114A1

公开(公告)日：2011-05-05

申请号：US13006068

申请日：2011-01-13

Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G11C16/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06K19/073

CPC classification number: G11C16/0483

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

公开(公告)号：US20080195893A1

公开(公告)日：2008-08-14

申请号：US11845194

申请日：2007-08-27

Applicant: Byeong Hoon LEE ,  Ki Hong KIM ,  Seung Won LEE ,  Sun Kwon KIM

Inventor： Byeong Hoon LEE ,  Ki Hong KIM ,  Seung Won LEE ,  Sun Kwon KIM

IPC: G06F11/00

CPC classification number: G06F11/1417 ,  G11C29/82

Abstract: A repairable semiconductor memory device including a memory cell array having a first block to store first system data and a second block to store second system data identical to the first system data. A controller transmits the first system data to a memory unit in response to a reset signal output from a host and the second system data to the memory unit based on a fail detection signal generated by an ECC detection block. The ECC detection block determines whether the first system data is defective. When a defect is generated in the first system data during resetting of the semiconductor memory device, the first system data is repaired by supplying the second system data.

Abstract translation: 一种可修复半导体存储器件，包括具有存储第一系统数据的第一块的存储单元阵列和用于存储与第一系统数据相同的第二系统数据的第二块。 控制器响应于从主机输出的复位信号将第一系统数据发送到存储器单元，并且基于由ECC检测块产生的故障检测信号将第二系统数据传送到存储器单元。 ECC检测块确定第一系统数据是否有缺陷。 当在半导体存储器件复位期间在第一系统数据中产生缺陷时，通过提供第二系统数据来修复第一系统数据。

公开(公告)号：US20080184086A1

公开(公告)日：2008-07-31

申请号：US11830461

申请日：2007-07-30

Applicant: Sun Kwon Kim ,  Byeong Hoon Lee ,  Ki Hong Kim ,  Seung Won Lee

Inventor： Sun Kwon Kim ,  Byeong Hoon Lee ,  Ki Hong Kim ,  Seung Won Lee

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/1068

Abstract: A buffer memory includes a memory cell array, a flag cell array, and a error correction block. The memory cell array has a plurality of word lines. Each of the plurality of word lines are electrically connected to a plurality of memory cells storing data. The flag cell array has a plurality of flag cells. Each of the plurality of flag cells is connected to each of the word lines and stores information that indicates whether error correction of the data has been performed. The error correction block performs error correction on the data output from the memory cell array in response to a command received through a host interface and flag data output from the flag cell array.

Abstract translation: 缓冲存储器包括存储单元阵列，标志单元阵列和纠错块。 存储单元阵列具有多个字线。 多个字线中的每一个电连接到存储数据的多个存储单元。 标志单元阵列具有多个标志单元。 多个标志单元中的每一个连接到每个字线，并且存储指示是否已经执行了数据的纠错的信息。 误差校正块响应于通过主机接口接收的命令和从标志单元阵列输出的标志数据对从存储器单元阵列输出的数据执行纠错。