公开(公告)号：US07566574B2

公开(公告)日：2009-07-28

申请号：US11850678

申请日：2007-09-06

申请人： Chen-Hsiung Yang

发明人： Chen-Hsiung Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/2007 ,  B81B2203/0127 ,  B81C1/00603 ,  B81C2201/019

摘要： A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.

摘要翻译： 提供了一种执行双面处理的方法。 首先，提供具有布置在前表面上的结构图案的晶片。 接着，在结构图案上限定多个前划线，并将填充层填充到前划线中。 接着，用结合层将结构图形结合到载体晶片上，并且在晶片的背面形成多个后划线。 最后，去除填充在前划痕线中的填充层。

公开(公告)号：US07505118B2

公开(公告)日：2009-03-17

申请号：US10711882

申请日：2004-10-12

申请人： Chen-Hsiung Yang

发明人： Chen-Hsiung Yang

IPC分类号： G03B27/58 ,  H01L21/683

CPC分类号： G03F7/70691 ,  G03F7/70425 ,  G03F7/70708 ,  G03F9/7003

摘要： A wafer carrier for carrying a wafer includes a transparent base and a conducting layer. The transparent base has dimensions similar to that of the wafer, and bonds the wafer with a bonding layer. The conducting layer is transparent, and can be attracted by an electrostatic chuck so that the electrostatic chuck can deliver the wafer.

摘要翻译： 用于承载晶片的晶片载体包括透明基底和导电层。 透明基底具有与晶片相似的尺寸，并且用晶片结合层。 导电层是透明的，并且可以被静电吸盘吸引，使得静电卡盘可以输送晶片。

公开(公告)号：US20060057775A1

公开(公告)日：2006-03-16

申请号：US10904621

申请日：2004-11-19

申请人： Shih-Feng Shao ,  Chen-Hsiung Yang ,  Hsin-Ya Peng

发明人： Shih-Feng Shao ,  Chen-Hsiung Yang ,  Hsin-Ya Peng

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of forming a wafer backside interconnecting wire includes forming a mask layer on the back surface, the mask layer including at least an opening corresponding to the bonding pad, performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to form a recess, removing the mask layer, and forming an interconnecting wire on the back surface.

摘要翻译： 形成晶片背面互连线的方法包括在背面形成掩模层，掩模层至少包括与焊盘对应的开口，从后表面进行第一蚀刻工艺以除去未被掩模保护的晶片 以形成凹部，去除掩模层，以及在背面上形成互连丝。

公开(公告)号：US07297610B2

公开(公告)日：2007-11-20

申请号：US11160975

申请日：2005-07-18

申请人： Chen-Hsiung Yang

发明人： Chen-Hsiung Yang

IPC分类号： H01L21/30

CPC分类号： H01L21/78

摘要： First, a device wafer having a substrate layer and a device layer is provided. Then, a first mask pattern is utilized to remove the device layer uncovered by the first mask pattern. Subsequently, a medium layer is formed on the surface of the device wafer, and the medium layer is then bonded to a carrier wafer. Thereafter, a second mask pattern is utilized to remove the substrate layer uncovered by the second mask pattern. Finally, the medium layer is separated from the carrier wafer, the substrate layer is bonded to an extendable film, and the medium layer is then removed.

摘要翻译： 首先，提供具有基板层和器件层的器件晶片。 然后，使用第一掩模图案来去除由第一掩模图案未覆盖的器件层。 随后，在器件晶片的表面上形成介质层，然后将介质层接合到载体晶片。 此后，利用第二掩模图案来去除未被第二掩模图案覆盖的基底层。 最后，将介质层与载体晶片分离，将基底层粘合到可延伸的膜上，然后除去介质层。

公开(公告)号：US07256128B2

公开(公告)日：2007-08-14

申请号：US10711883

申请日：2004-10-12

申请人： Chen-Hsiung Yang

发明人： Chen-Hsiung Yang

IPC分类号： H01L21/311

CPC分类号： B81C1/00571

摘要： A wafer, having at least a spindle region and at least two through regions alongside the spindle region, is provided. The wafer in the spindle region is partially removed from the bottom surface. Thereafter, the bottom surface is bonded to a carrier with a bonding layer, and the wafer in the through regions is completely removed from the top surface.

摘要翻译： 提供了具有至少一个主轴区域和沿主轴区域的至少两个贯通区域的晶片。 主轴区域中的晶片从底表面部分地移除。 此后，底面通过接合层与载体接合，贯通区域的晶片从顶面完全除去。

公开(公告)号：US20070158829A1

公开(公告)日：2007-07-12

申请号：US11434733

申请日：2006-05-17

申请人： Yuan-Chin Hsu ,  Chen-Hsiung Yang

发明人： Yuan-Chin Hsu ,  Chen-Hsiung Yang

IPC分类号： H01L23/52 ,  H01L23/34 ,  H01L21/00

CPC分类号： H01L23/49811 ,  H01L23/13 ,  H01L23/498 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： The present invention provides a connecting module having at least one passive component including a substrate, a connecting wire layout, at least one passive component and a chip-setting area, wherein the connecting wire layout is formed on the substrate, the passive components are formed on the connecting wire layout to electrically connect to the connecting wire layout. The chip-setting areas are formed in the substrate locating at different areas from the connecting wire layout, wherein the size of the passive components can be adjusted to match the needed impedance, and the numbers and the location of the chip-setting areas can be adjusted dynamically for reducing the dimension of the module.

摘要翻译： 本发明提供了一种具有至少一个无源元件的连接模块，包括基板，连接线布局，至少一个无源元件和芯片设置区域，其中连接线布局形成在基板上，形成无源元件 在连接线布局上电连接到连接线布局。 芯片设置区域形成在位于与连接布线布局不同的区域的基板中，其中可以调节无源部件的尺寸以匹配所需的阻抗，芯片设置区域的数量和位置可以是 动态调整以减少模块的尺寸。

公开(公告)号：US07045463B2

公开(公告)日：2006-05-16

申请号：US10904188

申请日：2004-10-28

申请人： Chen-Hsiung Yang

发明人： Chen-Hsiung Yang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： B81C1/00587

摘要： A method of etching cavities having different aspect ratios. An etching stop layer is formed on the bottom surface of a substrate, and a mask pattern is formed on the top surface of the substrate. The mask pattern includes a plurality of sacrificial patterns positioned on both a first cavity predetermined region and a second cavity predetermined region. Then, an etching process is performed to remove the substrate not covered by the mask layer. Then, the etching stop layer is removed, as well as the sacrificial patterns and the substrate covered by the sacrificial patterns.

摘要翻译： 蚀刻具有不同纵横比的腔的方法。 在基板的底面形成有蚀刻停止层，在基板的上表面形成有掩模图案。 掩模图案包括定位在第一空腔预定区域和第二空腔预定区域两者上的多个牺牲图案。 然后，进行蚀刻处理以去除未被掩模层覆盖的衬底。 然后，去除蚀刻停止层，以及由牺牲图案覆盖的牺牲图案和基板。

公开(公告)号：US20060030130A1

公开(公告)日：2006-02-09

申请号：US10711997

申请日：2004-10-19

申请人： Shih-Feng Shao ,  Chen-Hsiung Yang ,  Hsin-Ya Peng

发明人： Shih-Feng Shao ,  Chen-Hsiung Yang ,  Hsin-Ya Peng

IPC分类号： H01L21/78 ,  H01L21/50

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

摘要： A wafer supported by a carrier is provided where a bonding layer and an extendable film are disposed in between the carrier and the wafer. Then, a photoresist pattern is formed on a surface of the wafer to define scribe lines of the wafer. Following that, an anisotropic etching process is performed to remove the wafer uncovered by the photoresist pattern to form a plurality of dies. Finally the bonding layer is separated from the carrier.

摘要翻译： 提供了由载体支撑的晶片，其中结合层和可延伸膜设置在载体和晶片之间。 然后，在晶片的表面上形成光致抗蚀剂图案，以限定晶片的划线。 接着，进行各向异性蚀刻处理以除去由光致抗蚀剂图案未覆盖的晶片以形成多个管芯。 最后，结合层与载体分离。

公开(公告)号：US20060024965A1

公开(公告)日：2006-02-02

申请号：US10904188

申请日：2004-10-28

申请人： Chen-Hsiung Yang

发明人： Chen-Hsiung Yang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： B81C1/00587

摘要： A method of etching cavities having different aspect ratios. An etching stop layer is formed on the bottom surface of a substrate, and a mask pattern is formed on the top surface of the substrate. The mask pattern includes a plurality of sacrificial patterns positioned on both a first cavity predetermined region and a second cavity predetermined region. Then, an etching process is performed to remove the substrate not covered by the mask layer. Then, the etching stop layer is removed, as well as the sacrificial patterns and the substrate covered by the sacrificial patterns.

公开(公告)号：US20060021965A1

公开(公告)日：2006-02-02

申请号：US10711883

申请日：2004-10-12

申请人： Chen-Hsiung Yang

发明人： Chen-Hsiung Yang

IPC分类号： B44C1/22 ,  H01L21/30

CPC分类号： B81C1/00571

摘要： A wafer, having at least a spindle region and at least two through regions alongside the spindle region, is provided. The wafer in the spindle region is partially removed from the bottom surface. Thereafter, the bottom surface is bonded to a carrier with a bonding layer, and the wafer in the through regions is completely removed from the top surface.

摘要翻译： 提供了具有至少一个主轴区域和沿主轴区域的至少两个贯通区域的晶片。 主轴区域中的晶片从底表面部分地移除。 此后，底面通过接合层与载体接合，贯通区域的晶片从顶面完全除去。