公开(公告)号：US08125031B2

公开(公告)日：2012-02-28

申请号：US13100449

申请日：2011-05-04

Applicant: Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

Inventor： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC: H01L29/02

Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

公开(公告)号：US20090256183A1

公开(公告)日：2009-10-15

申请号：US12102608

申请日：2008-04-14

Applicant: Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

Inventor： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC: H01L27/105 ,  H01L21/8239

CPC classification number: H01L29/6659 ,  H01L27/11558 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/788

Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.

公开(公告)号：US20140054656A1

公开(公告)日：2014-02-27

申请号：US13594296

申请日：2012-08-24

Applicant: Chieh-Chih Chen ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

Inventor： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a device region, a first doped region and a gate structure. The first doped region is formed in the substrate adjacent to the device region. The gate structure is on the first doped region. The first doped region is overlapped the gate structure.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，器件区域，第一掺杂区域和栅极结构。 第一掺杂区域形成在与器件区域相邻的衬底中。 栅极结构在第一掺杂区域上。 第一掺杂区域与栅极结构重叠。

公开(公告)号：US20130207191A1

公开(公告)日：2013-08-15

申请号：US13369643

申请日：2012-02-09

Applicant: Chien-Chih Chen ,  Li-Fan Chen ,  Cheng-Chi Lin ,  Shin-Chin Lien ,  Shyi-Yuan Wu

Inventor： Chien-Chih Chen ,  Li-Fan Chen ,  Cheng-Chi Lin ,  Shin-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L29/78 ,  H01L21/30

CPC classification number: H01L27/027 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/861

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a first doped region and a second doped region. The first doped region comprises a first contact region. The first doped region and the first contact region have a first type conductivity. The second doped region comprises a second contact region. The second doped region and the second contact region have a second type conductivity opposite to the first type conductivity. The first doped region is adjacent to the second doped region.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括第一掺杂区和第二掺杂区。 第一掺杂区域包括第一接触区域。 第一掺杂区域和第一接触区域具有第一类型的导电性。 第二掺杂区域包括第二接触区域。 第二掺杂区域和第二接触区域具有与第一类型导电性相反的第二类型导电性。 第一掺杂区域与第二掺杂区域相邻。

公开(公告)号：US20130020680A1

公开(公告)日：2013-01-24

申请号：US13185948

申请日：2011-07-19

Applicant: Chieh-Chih Chen ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

Inventor： Chieh-Chih Chen ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L29/866 ,  H01L21/22

CPC classification number: H01L29/66106 ,  H01L27/0629 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/7835 ,  H01L29/866

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括二极管。 二极管包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域具有第一导电类型。 第二掺杂区具有与第一导电类型相反的第二导电类型。 第二掺杂区域和第三掺杂区域通过第一掺杂区域彼此分离。 第三掺杂区域具有彼此相邻的第一部分和第二部分。 第一部分和第二部分分别与第二掺杂区域相邻并远离第二掺杂区域。 第一部分的掺杂剂浓度大于第二部分的掺杂剂浓度。

公开(公告)号：US20120280316A1

公开(公告)日：2012-11-08

申请号：US13101486

申请日：2011-05-05

Applicant: Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

Inventor： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0684 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/861

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括第一掺杂阱，第一掺杂电极，第二掺杂电极，掺杂条和掺杂顶区。 掺杂条在第一掺杂电极和第二掺杂电极之间的第一掺杂阱上。 掺杂的条带彼此分离。 掺杂的顶部区域在掺杂的条带上并且在掺杂条带之间的第一掺杂阱上延伸。 第一掺杂阱和掺杂顶区具有第一导电类型。 掺杂的条带具有与第一导电类型相反的第二导电类型。

公开(公告)号：US20120025352A1

公开(公告)日：2012-02-02

申请号：US12847467

申请日：2010-07-30

Applicant: Cheng-Chi Lin ,  Wei-Hsun Hsu ,  Shuo-Lun Tu ,  Shih-Chin Lien ,  Chin-Pen Yeh

Inventor： Cheng-Chi Lin ,  Wei-Hsun Hsu ,  Shuo-Lun Tu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC: H01L29/73

CPC classification number: H01L29/7322 ,  H01L29/0692

Abstract: A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other.

Abstract translation: 包括基极区域，发射极区域和集电极区域的双极结型晶体管（BJT）器件包括衬底，衬底中的深阱区域，深阱区域中用作基极区域的第一阱区域，第二 阱区域作为集电极区域，第二阱区域和第一阱区域在其间形成第一接合部，第一阱区域中的第一掺杂区域用作发射极区域，第一掺杂区域 并且所述第一阱区域在其间形成第二结，其中所述第一掺杂区域包括沿第一方向延伸的第一部分和沿与所述第一方向不同的第二方向延伸的第二部分，所述第一部分和所述第二部分与 彼此。

公开(公告)号：US20110140201A1

公开(公告)日：2011-06-16

申请号：US12775440

申请日：2010-05-06

Applicant: Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

Inventor： Cheng-Chi Lin ,  Chen-Yuan Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66689

Abstract: A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor.

Abstract translation: 描述具有低比导通电阻的横向功率MOSFET。 铰接圆弧形图案中堆叠的P顶和N级区分离晶体管的源极和漏极。

公开(公告)号：US20070108520A1

公开(公告)日：2007-05-17

申请号：US11399427

申请日：2006-04-07

Applicant: Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

Inventor： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

Abstract translation: 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US08921933B2

公开(公告)日：2014-12-30

申请号：US13111018

申请日：2011-05-19

Applicant: Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

Inventor： Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7824 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

Abstract: A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region.

Abstract translation: 提供半导体结构及其操作方法。 半导体结构包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一沟槽结构和第二栅结构。 第一掺杂区域在衬底中。 第一掺杂区具有第一导电类型。 第二掺杂区域在第一掺杂区域中。 第二掺杂区具有与第一导电类型相反的第二导电类型。 具有第一导电类型的第三掺杂区域在第二掺杂区域中。 第一沟槽结构具有第一栅极结构。 第一栅极结构和第二栅极结构分别位于第二掺杂区域的不同侧。