公开(公告)号：US6107155A

公开(公告)日：2000-08-22

申请号：US131118

申请日：1998-08-07

Applicant: Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10873

Abstract: A modified method for forming stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. First openings are etched for capacitor node contacts. A polysilicon layer is deposited and etched back to form node contacts in the first openings, which are generally recessed due to overetching to completely remove the polysilicon on the insulating surface. A Si.sub.3 N.sub.4 etch-stop layer is deposited to protect the exposed sidewalls in the first openings. A disposable second SiO.sub.2 insulating layer is deposited and second openings are etched over and to the node contacts for forming bottom electrodes. A conformal second polysilicon layer is deposited and chemically/mechanically polished back to form the bottom electrodes in the second openings. The second insulating layer is removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the Si.sub.3 N.sub.4 on the sidewalls protects the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are now completed by forming an inter-electrode dielectric layer on the bottom electrodes, and depositing and patterning a third polysilicon layer for top electrodes.

Abstract translation: 描述了一种用于形成用于DRAM的堆叠电容器的修改方法，其规避了由于未对准引起的氧化物侵蚀。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。 第一个开口蚀刻电容器节点触点。 沉积多晶硅层并将其回蚀刻以形成第一开口中的节点接触，其通常由于过蚀刻而凹陷以完全去除绝缘表面上的多晶硅。 沉积Si 3 N 4蚀刻停止层以保护第一开口中暴露的侧壁。 沉积一次性第二SiO 2绝缘层，并且在节点触点上蚀刻第二开口并形成底部电极。 沉积保形第二多晶硅层并在第二开口中化学/机械抛光以形成底部电极。 通过湿法蚀刻去除蚀刻停止层来除去第二绝缘层。 当第二开口在节点接触开口上不对准时，侧壁上的Si 3 N 4保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 现在通过在底部电极上形成电极间电介质层，并沉积和构图顶部电极的第三多晶硅层来完成电容器。

公开(公告)号：US6037213A

公开(公告)日：2000-03-14

申请号：US89550

申请日：1998-06-03

Applicant: Cheng-Yeh Shih ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Cheng-Yeh Shih ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for making cylinder-shaped stacked capacitors for DRAMs is described. A planar first insulating layer is formed over device areas. An etch-stop layer, a second insulating layer, and a polish-back endpoint detect layer are deposited in which cylinder-shaped capacitors with node contacts are formed. First openings for node contacts are etched in the polish-back and second insulating layers to the etch-stop layer aligned over the device areas. Wider second openings, aligned over the first openings, are etched through the polish-back layer, and also removes the etch-stop layer in the first openings. The second insulating layer in the second openings is etched to the etch-stop layer, while the first insulating layer is etched in the first openings for node contact openings. A doped first polysilicon layer is deposited and polished back to the polish-back detect layer to form concurrently the node contacts in the first openings and bottom electrodes in the second openings. The second insulating layer is removed by a wet etch. A thin dielectric layer is deposited, and top electrodes are formed from a second polysilicon layer. The etch-stop layer provides better control of the etching depth for the first and second openings that improves reliability while providing a simple manufacturing process.

Abstract translation: 描述了一种用于制造用于DRAM的圆柱形叠层电容器的方法。 在器件区域上形成平面的第一绝缘层。 沉积有蚀刻停止层，第二绝缘层和抛光端点检测层，其中形成具有节点接触的圆柱形电容器。 用于节点接触的第一开口在抛光和第二绝缘层中蚀刻到在器件区域上对准的蚀刻停止层。 在第一开口上对准的更宽的第二开口被蚀刻穿过抛光层，并且还去除第一开口中的蚀刻停止层。 将第二开口中的第二绝缘层蚀刻到蚀刻停止层，同时在用于节点接触开口的第一开口中蚀刻第一绝缘层。 掺杂的第一多晶硅层被沉积并抛光回到抛光检测层，以同时形成第二开口中的第一开口和底部电极中的节点接触。 通过湿蚀刻去除第二绝缘层。 沉积薄介电层，并且顶电极由第二多晶硅层形成。 蚀刻停止层提供对第一和第二开口的蚀刻深度的更好控制，其在提供简单的制造工艺的同时提高了可靠性。

公开(公告)号：US6033981A

公开(公告)日：2000-03-07

申请号：US358988

申请日：1999-07-22

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu

IPC: H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/31116 ,  H01L21/31612

Abstract: A method to eliminate voids in the dielectric oxide between closely spaced conducting lines is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A high density plasma (HDP) dielectric layer is deposited overlying the conductive lines and the substrate. The HDP layer is etched through to expose the edges of the conducting lines. An insulating layer is deposited overlying the HDP layer and conducting lines. A chemical mechanical polishing (CMP) is used to remove the peaks of the insulating layer, exposing the HDP layer in the area overlying the conducting lines. The exposed HDP layer is etched away exposing the top surface of the conducting lines. The insulating layer is then selectively etched away. Spacers may then be added along the sidewalls of the conductor. Finally, a second HDP layer is deposited overlying the first dielectric layer and conducting lines free from voids. The integrated circuit device is completed.

Abstract translation: 实现了在紧密间隔的导电线之间消除电介质氧化物中的空隙的方法。 提供基板。 在基板上设置窄间隔的导线。 沉积在导电线和衬底上的高密度等离子体（HDP）电介质层。 HDP层被蚀刻通过以暴露导线的边缘。 绝缘层沉积在HDP层和导线上。 使用化学机械抛光（CMP）去除绝缘层的峰，使覆盖导电线的区域中的HDP层暴露。 暴露的HDP层被蚀刻掉，暴露导电线的顶表面。 然后选择性地蚀刻绝缘层。 然后可以沿着导体的侧壁添加间隔物。 最后，沉积第二HDP层，覆盖第一介电层和没有空隙的导电线。 集成电路装置完成。

公开(公告)号：US06403416B1

公开(公告)日：2002-06-11

申请号：US09226279

申请日：1999-01-07

Applicant: Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

Inventor： Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

IPC: H01L218242

CPC classification number: H01L28/91

Abstract: A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.

Abstract translation: 描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。 第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。 沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。 沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。 使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。 沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。 在热磷酸中除去第一和第二Si 3 N 4层。 电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。

公开(公告)号：US6080647A

公开(公告)日：2000-06-27

申请号：US34927

申请日：1998-03-05

Applicant: Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

Inventor： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC: H01L21/336 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US6042999A

公开(公告)日：2000-03-28

申请号：US73952

申请日：1998-05-07

Applicant: Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

Inventor： Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/26

CPC classification number: H01L21/76808 ,  G03F7/0035 ,  H01L21/0276

Abstract: A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.

Abstract translation: 公开了一种稳健的双镶嵌工艺，其中通过在形成镶嵌导电线开口之前通过填充具有保护材料的接触或通孔开口来保护衬底中的子结构免受由镶嵌工艺中所需的多次蚀刻所造成的损伤 具有分隔下电介质层和上电介质层的蚀刻停止层的结构。 在第一实施例中，在通过蚀刻形成上导电线开口之前，保护材料部分地从到达底层结构的开孔中去除。 在第二实施例中，在通过蚀刻形成上导电线开口的同时去除孔中的保护材料。 在第三个实施例中，应用所公开的工艺，而不需要用于本发明的双镶嵌工艺的蚀刻停止层。

公开(公告)号：US6015734A

公开(公告)日：2000-01-18

申请号：US148561

申请日：1998-09-04

Applicant: Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

Inventor： Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the polysilicon plugs abutting the Si.sub.3 N.sub.4 etch-stop layer protect the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are completed by forming a thin dielectric layer on the bottom electrodes, and forming top electrodes from a patterned third polysilicon layer.

Abstract translation: 实现了当底电极不对准节点接触时，用于形成具有提高的产量的DRAM的叠层电容器的新方法。 沉积平面氧化硅（SiO 2）第一绝缘层，Si 3 N 4蚀刻停止层和一次性第二绝缘层。 在绝缘层中蚀刻用于节点接触的第一开口。 沉积多晶硅层并回蚀刻以在第一开口中形成节点接触。 节点触点凹陷在第二绝缘层中，但在蚀刻停止层之上，以形成邻接蚀刻停止层的节点触点。 沉积一次性第三SiO 2层。 底部电极的第二个开口被蚀刻到节点触点上。 沉积保形的第二多晶硅层，并在第二开口中化学/机械抛光以形成底部电极。 第三绝缘层和第二绝缘层通过湿法蚀刻去除蚀刻停止层。 当第二开口在节点接触开口上不对准时，邻接Si 3 N 4蚀刻停止层的多晶硅栓保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 通过在底部电极上形成薄的电介质层，并从图案化的第三多晶硅层形成顶部电极来完成电容器。

公开(公告)号：US08820385B2

公开(公告)日：2014-09-02

申请号：US13468299

申请日：2012-05-10

Applicant: Cheng-Ming Wu

Inventor： Cheng-Ming Wu

IPC: E06B9/305

CPC classification number: E06B9/322 ,  E06B2009/3222

Abstract: Disclosed is a control device for a cordless blind with willful stop at any positions according to user needs during switching operation. The control device primarily comprises a force-return mechanism, a shaft connector, and a braking buffer mechanism which are all installed inside a same housing. The force-return mechanism has a flat spring bevel gear and an elastic element. One end of the shaft connector is a transmission bevel gear meshed with the flat spring bevel gear. The braking buffer mechanism includes a friction ring and an impeding spring where the friction ring is immovably fixed inside the housing with a wear-proof annular inwall. The impeding spring is tightly plugged into the friction ring with an extrusion to prevent the rotation of the transmission bevel gear. Specifically, the shaft connector has a trigger to change the friction between the impeding spring and the friction ring.

Abstract translation: 本发明公开了一种无绳盲板的控制装置，其在切换操作期间根据用户需要在任意位置故意停止。 控制装置主要包括一个力回复机构，一个轴连接器和一个制动缓冲机构，它们均安装在同一个外壳内。 力回复机构具有扁平的弹簧锥齿轮和弹性元件。 轴连接器的一端是与扁平弹簧伞齿轮啮合的传动伞齿轮。 制动缓冲机构包括摩擦环和阻挡弹簧，其中摩擦环通过耐磨环形壁固定在壳体内。 阻碍弹簧用挤压件紧密地插入摩擦环中，以防止变速器锥齿轮的旋转。 具体地，轴连接器具有用于改变阻力弹簧和摩擦环之间的摩擦力的触发器。

公开(公告)号：US06436763B1

公开(公告)日：2002-08-20

申请号：US09498738

申请日：2000-02-07

Applicant: Jenn Ming Huang ,  Yu-Hua Lee ,  Cheng Ming Wu

Inventor： Jenn Ming Huang ,  Yu-Hua Lee ,  Cheng Ming Wu

IPC: H01L218242

CPC classification number: H01L27/10888 ,  H01L27/10811 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/90

Abstract: A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography while providing openings to bit line contacts between closely spaced capacitors. A bottom antireflecting coating (BARC) is used in a first method; a non-conform PECVD oxide is used in a second method to make reliable high aspect ratio openings between the capacitors. The BARC is deposited to fill the space between capacitors. A photo-resist layer with improved uniformity is then deposited over the BARC and exposed and developed to form an etch mask with improved resolution for the capacitor top plate. The BARC is plasma etched, and the polysilicon plate is patterned. In the second method a non-conformal PECVD oxide is deposited that is thicker on the top of the capacitors than in the narrow space between capacitors. The PECVD oxide is anisotropically etched back to form self-aligned openings over the bit line contacts, and openings are etched in the polysilicon capacitor top plate aligned over the bit line contact openings. A photoresist etch mask is then used to complete the patterning of the top plate.

Abstract translation: 实现了具有逻辑电路的用于制造电容器下位线（CUB）DRAM的方法。 CUB比电容器位线（COB）DRAM电路更好，因为接触宽高比减小，但是CUB需要在电容器粗糙的形状图上形成电容器顶板，同时为紧密间隔的电容器之间的位线接触提供开口。 在第一种方法中使用底部抗反射涂层（BARC）; 在第二种方法中使用不合格的PECVD氧化物，以在电容器之间形成可靠的高纵横比开口。 BARC存放以填补电容器之间的空间。 然后将具有改善的均匀性的光致抗蚀剂层沉积在BARC上，并暴露和显影以形成具有改进的用于电容器顶板的分辨率的蚀刻掩模。 BARC被等离子体蚀刻，多晶硅板被图案化。 在第二种方法中，沉积在电容器顶部比在电容器之间的狭窄空间中更厚的非共形PECVD氧化物。 PECVD氧化物被各向异性地回蚀以在位线触点上形成自对准的开口，并且在多晶硅电容器顶板上蚀刻开口，在位线接触开口上对齐。 然后使用光致抗蚀剂蚀刻掩模来完成顶板的图案化。

公开(公告)号：US06365325B1

公开(公告)日：2002-04-02

申请号：US09247791

申请日：1999-02-10

Applicant: Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

Inventor： Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

IPC: G03C500

CPC classification number: G03F7/40

Abstract: A method for fabricating a microelectronic layer. There is first provided a substrate. There is then formed over the substrate a target layer. There is then formed upon the target layer a patterned photoresist layer which defines a first aperture, where the first aperture has a first aperture width which exposes a first portion of the target layer. There is then reflowed thermally the patterned photoresist layer to form a reflowed patterned photoresist layer which defines a substantially straight sided second aperture. The second aperture has a second aperture width less than the first aperture width, and the second aperture thus exposes a second portion of the blanket target layer of areal dimension less than the first portion of the blanket target layer. Finally, there is then fabricated the target layer to form a fabricated target layer while employing the reflowed patterned photoresist layer as a mask layer. The method is useful insofar as it allows the target layer to be fabricated while avoiding the use of advanced microelectronic fabrication photolithographic tooling when forming the patterned photoresist layer.

Abstract translation: 一种制造微电子层的方法。 首先提供基板。 然后在衬底上形成靶层。 然后在目标层上形成限定第一孔的图案化光致抗蚀剂层，其中第一孔具有暴露目标层的第一部分的第一孔宽度。 然后将图案化的光致抗蚀剂层热回流以形成限定基本上直的第二孔的回流图案化光致抗蚀剂层。 第二孔径具有小于第一孔径宽度的第二孔径宽度，并且第二孔口因此暴露了覆盖层目标层的面积尺寸小于覆盖层目标层的第一部分的第二部分。 最后，然后制造目标层以形成制造的目标层，同时使用回流图案化的光致抗蚀剂层作为掩模层。 该方法是有用的，只要它允许制造目标层，同时避免在形成图案化的光致抗蚀剂层时使用先进的微电子制造光刻工具。