公开(公告)号：US4940910A

公开(公告)日：1990-07-10

申请号：US360511

申请日：1989-06-02

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G05F1/46

CPC classification number: G05F1/466 ,  Y10S323/907

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Abstract translation: 可以在单片集成电路中制造的类型的温度和处理补偿时间延迟电路利用连接到充电电容器（14）的端子的场效应晶体管（FET）（12）。 连接到FET（12）的栅极的偏置电压随着温度而变化，以补偿由于温度变化而从电容器（14）流过FET（12）的电流的变化。 偏置电压也可以从一个集成电路到另一个集成电路的变化，以补偿由集成电路的处理变化引起的FET阈值电压的变化。

公开(公告)号：US4912435A

公开(公告)日：1990-03-27

申请号：US404943

申请日：1989-09-07

Applicant: Clark R. Williams ,  Ching-Lin Jiang

Inventor： Clark R. Williams ,  Ching-Lin Jiang

IPC: H03B5/36 ,  H03K3/014 ,  H03K3/354 ,  H03L3/00

CPC classification number: H03B5/06 ,  H03B5/364 ,  H03K3/014 ,  H03K3/3545 ,  H03L3/00 ,  H03B2200/0012

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract translation: 一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。 这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

公开(公告)号：US4873665A

公开(公告)日：1989-10-10

申请号：US203424

申请日：1988-06-07

Applicant: Ching-Lin Jiang ,  Clark R. Williams

Inventor： Ching-Lin Jiang ,  Clark R. Williams

IPC: G06F5/06 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C19/28

CPC classification number: G11C11/412 ,  G06F5/065 ,  G11C11/41 ,  G11C19/287 ,  G11C8/16

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract translation: 双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。 第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管 或与每个双存储单元相关联的位线。

公开(公告)号：US4654829A

公开(公告)日：1987-03-31

申请号：US682701

申请日：1984-12-17

Applicant: Ching-Lin Jiang ,  Robert D. Lee

Inventor： Ching-Lin Jiang ,  Robert D. Lee

IPC: G11C5/00 ,  G11C5/14 ,  G11C7/24 ,  G11C13/00

CPC classification number: G11C5/141 ,  G11C5/00 ,  G11C7/24

Abstract: A portable, non-volatile read/write memory module includes a battery for providing standby power that is coupled to a monolithic integrated circuit. Five terminals of the module are removably connected to a host electronic system for transfer of data to and from the module. One of the terminals is a chip enable input that may optionally be used for providing operating power to the monolithic integrated circuit. The monolithic integrated circuit further includes control circuitry that may optionally be coded for providing a security feature for access to data stored in the memory module.

Abstract translation: 便携式非易失性读/写存储器模块包括用于提供耦合到单片集成电路的待机功率的电池。 模块的五个端子可拆卸地连接到主机电子系统，用于将数据传送到模块和从模块传输数据。 其中一个端子是芯片使能输入，其可以可选地用于向单片集成电路提供工作电源。 单片集成电路还包括控制电路，其可选地被编码以提供用于访问存储在存储器模块中的数据的安全特征。

公开(公告)号：US4535427A

公开(公告)日：1985-08-13

申请号：US447348

申请日：1982-12-06

Applicant: Ching-Lin Jiang

Inventor： Ching-Lin Jiang

IPC: G06F5/10 ,  G11C8/04 ,  G11C11/40

CPC classification number: G06F5/10 ,  G11C8/04

Abstract: A FIFO memory chip includes read and write pointers in the form of an X and a Y shift register carrying a pair of pointer bits that point to a memory cell in a rectangular cell array.

Abstract translation: FIFO存储器芯片包括X和Y移位寄存器的形式的读指针和Y指针，Y移位寄存器携带指向矩形单元阵列中的存储单元的一对指针位。