公开(公告)号：US08236659B2

公开(公告)日：2012-08-07

申请号：US12816519

申请日：2010-06-16

Applicant: Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

Inventor： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC: H01L21/336

CPC classification number: H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US08216906B2

公开(公告)日：2012-07-10

申请号：US12827344

申请日：2010-06-30

Applicant: Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

Inventor： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过形成用作蚀刻停止的轻掺杂源极和漏极（LDD）区域来实现改进的控制。 LDD区域可以在蚀刻工艺期间用作蚀刻停止层，以在衬底中形成限定器件的源极和漏极区域的凹陷。

公开(公告)号：US20120056276A1

公开(公告)日：2012-03-08

申请号：US12875834

申请日：2010-09-03

Applicant: Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

Inventor： Chun-Fai Cheng ,  Ka-Hing Fung ,  Shyh-Wei Wang ,  Chin-Te Su

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

Abstract: The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

Abstract translation: 本公开提供半导体器件及其制造方法，其中半导体器件具有应变的不对称源极和漏极区域。 制造半导体器件的方法包括提供衬底并在衬底上形成多晶硅叠层。 掺杂剂以垂直于衬底的约10°至约25°的注入角度注入衬底中。 邻近衬底上的多晶硅叠层形成间隔物。 源极区和漏极区被蚀刻在衬底中。 应变源极层和应变漏极层分别沉积在衬底中的蚀刻源极和漏极区域中，使得源极区域和漏极区域相对于多晶硅栅极叠层是不对称的。 多晶硅堆叠从衬底去除，并且使用去除多晶硅叠层的最后工艺形成高k金属栅极。

公开(公告)号：US09799750B2

公开(公告)日：2017-10-24

申请号：US13551107

申请日：2012-07-17

Applicant: Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

Inventor： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

IPC: H01L29/772 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

公开(公告)号：US20130299910A1

公开(公告)日：2013-11-14

申请号：US13469526

申请日：2012-05-11

Applicant: Chun-Fai Cheng ,  Bwo-Ning Chen ,  Chin-Te Su ,  Huang-Sheng Ho

Inventor： Chun-Fai Cheng ,  Bwo-Ning Chen ,  Chin-Te Su ,  Huang-Sheng Ho

IPC: H01L27/088 ,  H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.

Abstract translation: 公开了一种用于控制IC器件应变的方法和由此形成的器件。 示例性实施例包括接收具有对应于IC器件的器件区域的IC器件衬底。 在器件区域内形成非晶区域的器件区域上进行注入工艺。 IC器件衬底被凹入以在器件区域中限定具有由非晶区域的无定形结构确定的分布的源极/漏极凹部。 然后进行源极/漏极外延，以在源极/漏极凹部内形成源极/漏极结构。

公开(公告)号：US08445940B2

公开(公告)日：2013-05-21

申请号：US13543943

申请日：2012-07-09

Applicant: Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

Inventor： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC: H01L31/072

CPC classification number: H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

Abstract: An integrated circuit device is disclosed. The disclosed device provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device disclosed herein has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a {100} crystallographic plane of the substrate.

Abstract translation: 公开了一种集成电路器件。 所公开的装置提供对集成电路装置的表面接近度和尖端深度的改进的控制。 本文公开的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

公开(公告)号：US20130119444A1

公开(公告)日：2013-05-16

申请号：US13296908

申请日：2011-11-15

Applicant: Chun-Fai CHENG ,  An-Shen CHANG ,  Hui-Min LIN ,  Tsz-Mei KWOK ,  Hsien-Ching LO

Inventor： Chun-Fai CHENG ,  An-Shen CHANG ,  Hui-Min LIN ,  Tsz-Mei KWOK ,  Hsien-Ching LO

IPC: H01L29/772 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L21/02639 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法包括在衬底中形成具有初始底表面的楔形凹部; 将楔形凹部转变成具有大于楔形凹部的高度的高度的扩大凹部; 并在扩大的凹部中外延生长应变材料。

公开(公告)号：US08368147B2

公开(公告)日：2013-02-05

申请号：US12761949

申请日：2010-04-16

Applicant: Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

Inventor： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC: H01L21/70

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

Abstract translation: 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。

公开(公告)号：US20120091539A1

公开(公告)日：2012-04-19

申请号：US12905579

申请日：2010-10-15

Applicant: Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

Inventor： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

Abstract translation: 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。

公开(公告)号：US20120001238A1

公开(公告)日：2012-01-05

申请号：US12827344

申请日：2010-06-30

Applicant: Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

Inventor： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC: H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过形成用作蚀刻停止的轻掺杂源极和漏极（LDD）区域来实现改进的控制。 LDD区域可以在蚀刻工艺期间用作蚀刻停止层，以在衬底中形成限定器件的源极和漏极区域的凹陷。