公开(公告)号：US07141845B2

公开(公告)日：2006-11-28

申请号：US10898706

申请日：2004-07-23

Applicant: Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

Inventor： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

IPC: H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

Abstract: Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

Abstract translation: 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

公开(公告)号：US07074660B2

公开(公告)日：2006-07-11

申请号：US10765910

申请日：2004-01-29

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A transistor fin of a fin field-effect transistor is arranged between two contact structures. A gate electrode encapsulating the transistor fin on three sides is caused to recede by means of a nonlithographic process from contact trenches, which define the contact structures, before the formation of the contact structures. A distance a between the gate electrode and the contact structures is not subject to any tolerances due to the overlay of two independent lithographic masks. For a given extent of the gate electrode along the transistor fin, it is possible to minimize a distance A between the contact structures and thereby significantly increase the packing density of a plurality of fin field-effect transistors on a substrate compared with conventional devices.

Abstract translation: 翅片场效应晶体管的晶体管鳍片布置在两个接触结构之间。 在形成接触结构之前，通过非平版印刷工艺，从形成接触结构的接触沟槽中，将晶体管鳍片封装在三面上的栅电极被后退。 门电极和接触结构之间的距离a由于两个独立的光刻掩模的覆盖而不受任何公差的影响。 对于沿着晶体管鳍片的给定范围的栅电极，可以使接触结构之间的距离A最小化，从而与常规器件相比，显着增加了衬底上的多个鳍状场效应晶体管的堆积密度。

公开(公告)号：US07005346B2

公开(公告)日：2006-02-28

申请号：US10850960

申请日：2004-05-21

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/336

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/1087

Abstract: A memory cell has a vertical construction of a capacitor and a vertical FET arranged above the latter which can be produced with a lower outlay and in a technologically more reliable fashion. This is achieved by virtue of the fact that two first trenches running parallel and having a first depth are etched in the semiconductor substrate. Between the trenches is formed a web, which is connected to the semiconductor substrate at its narrow sides and which is severed at its underside and is separated from the semiconductor substrate. The suspended web is then provided with a closed dielectric. After a filling, the FET is applied and connected to the web as memory node.

Abstract translation: 存储单元具有垂直构造的电容器和布置在其上方的垂直FET，其可以以较低的开销和技术上更可靠的方式产生。 这是通过在半导体衬底中蚀刻平行且具有第一深度的两个第一沟槽来实现的。 在沟槽之间形成网状物，该网状物在其窄边连接到半导体衬底，并且在其下侧被切断并与半导体衬底分离。 然后，悬挂的网带有封闭的电介质。 填充后，施加FET并将其连接到作为存储器节点的网。

公开(公告)号：US07005240B2

公开(公告)日：2006-02-28

申请号：US10370857

申请日：2003-02-20

Applicant: Dirk Manger ,  Matthias Goldbach

Inventor： Dirk Manger ,  Matthias Goldbach

IPC: G03C5/00

CPC classification number: H01L21/0337

Abstract: A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in a projection process. The conformal deposition is etched back laterally on the elevated structures resulting in the spacer structures. The elevated structures between the spacer structures are subsequently etched away, so that the spacer structures remain in an isolated fashion as sublithographic structures of a hard mask with a doubled structure density compared with that originally produced in lithographic projection. In a regularly disposed two-dimensional array of structures in the hard mask for forming trenches—for instance for trench capacitors—the method achieves a doubling of the structure density in the array. A further iteration step is formed by forming further spacer structures on the first and second spacer structures, thereby achieving an even higher increase in structure density in the hard mask.

Abstract translation: 由间隔结构产生硬掩模。 间隔结构由在投影过程中光刻生成的升高结构上的共形沉积形成。 在升高的结构上横向蚀刻共形沉积物，导致间隔物结构。 间隔结构之间的升高的结构随后被蚀刻掉，使得间隔结构保持隔离的方式作为具有双重结构密度的硬掩模的亚光刻结构，与原始在光刻投影中产生的结合密度相比较。 在用于形成沟槽的硬掩模中的例如用于沟槽电容器的规则排列的二维结构阵列中，该方法实现阵列中结构密度的加倍。 通过在第一和第二间隔结构上形成另外的间隔结构形成另外的迭代步骤，从而在硬掩模中实现甚至更高的结构密度增加。

公开(公告)号：US06932916B2

公开(公告)日：2005-08-23

申请号：US10425179

申请日：2003-04-29

Applicant: Dirk Manger ,  Hans-Peter Moll ,  Till Schloesser

Inventor： Dirk Manger ,  Hans-Peter Moll ,  Till Schloesser

IPC: H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8242 ,  B44C1/22 ,  H01L21/302

CPC classification number: H01L21/3081 ,  H01L21/3083 ,  H01L21/76229 ,  H01L27/1087 ,  H01L29/66181

Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.

Abstract translation: 在半导体衬底上蚀刻具有不同深度的沟槽的方法包括：提供具有第一和第二开口的掩模。 第一和第二开口位于相应的第一和第二沟槽将被蚀刻的位置。 在对应于第二开口的位置处，在衬底上方设置由缓蚀刻材料制成的缓蚀刻区域。 当暴露于所选择的蚀刻剂时，以暴露于所选择的蚀刻剂的半导体衬底被蚀刻的速率小的速率蚀刻慢刻蚀材料。

公开(公告)号：US07678679B2

公开(公告)日：2010-03-16

申请号：US11414553

申请日：2006-05-01

Applicant: Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

Inventor： Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28247 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.

Abstract translation: 选择性地在垂直装置的垂直侧壁上生长的生长材料在垂直装置的基本上垂直的侧壁上形成侧壁间隔物，其设置在半导体衬底的水平衬底表面上。 可以在垂直装置的垂直侧壁上设置间隔物种子衬垫，以控制选择性生长。 垂直装置可以是场效应晶体管（FET）的栅电极。 利用选择性地生长的侧壁间隔物，FET的重掺杂接触区域可以与栅电极精确地间隔开。 重掺杂的接触区域与栅电极的距离不取决于栅电极的高度。 可以实现重掺杂接触区域和栅电极之间超过150nm的距离，以便于例如DMOS器件的形成。

公开(公告)号：US20090321940A1

公开(公告)日：2009-12-31

申请号：US12165093

申请日：2008-06-30

Applicant: Gerhard Kunkel ,  Dirk Manger ,  Stephan Wege

Inventor： Gerhard Kunkel ,  Dirk Manger ,  Stephan Wege

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/76802 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is described including a first and a second plurality of conductor lines, each of the lines being separated from an adjacent line by a spacer dielectric and capped with a first and second dielectric cap material, respectively. A contact element is embedded in a covering dielectric layer with electrical contact to one of the first plurality of conductor lines in a contact portion, while being separated from a line adjacent to the contacted line only by the second cap material.

Abstract translation: 描述了集成电路，其包括第一和第二多个导体线，每条线分别由隔离电介质与相邻线分开，并分别用第一和第二电介质盖材料封盖。 接触元件嵌入到覆盖电介质层中，其与接触部分中的第一多个导体线中的一个导电接触，同时仅通过第二帽材料与接触线相邻的线分离。

公开(公告)号：US20090239314A1

公开(公告)日：2009-09-24

申请号：US12051932

申请日：2008-03-20

Applicant: Martin Haberjahn ,  Sascha Dieter ,  Andrea Graf ,  Christoph Noelscher ,  Dirk Manger ,  Stephan Wege

Inventor： Martin Haberjahn ,  Sascha Dieter ,  Andrea Graf ,  Christoph Noelscher ,  Dirk Manger ,  Stephan Wege

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/26

Abstract: Methods of manufacturing a semiconductor device and an apparatus for the manufacturing of semiconductor devices are provided. An embodiment regards providing a process which changes the volume of at least one layer of a semiconductor substrate or of at least one layer deposited on the semiconductor substrate, and measuring a change in volume of such at least one layer using fluorescence. In another embodiment, a change in volume of such at least one layer is measured using reflection of electromagnetic waves.

Abstract translation: 提供制造半导体器件的方法和用于制造半导体器件的设备。 实施例涉及提供一种改变至少一层半导体衬底或沉积在半导体衬底上的至少一层的层的体积，并使用荧光来测量这样的至少一层的体积变化的过程。 在另一个实施例中，使用电磁波的反射来测量这样的至少一层的体积变化。

公开(公告)号：US07473952B2

公开(公告)日：2009-01-06

申请号：US11118768

申请日：2005-05-02

Applicant: Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

Inventor： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10876 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891

Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Abstract translation: 存储单元阵列包括其中形成有多个存储单元的多个有效区域。 存储单元包括存储电容器，至少部分地形成在具有衬底表面的半导体衬底中的晶体管，所述晶体管包括第一源极/漏极区域。 与衬底表面相邻形成的第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道区域。 第一源极/漏极区域邻近于衬底表面形成。 沟道区设置在半导体衬底和栅电极中。 有源区域的行通过沿着第一方向延伸的隔离槽相互分离。 第一和第二字线被布置在每行活动区域的任一侧面上。 第一和第二字线经由相应行的有效区域的晶体管的栅电极相互连接。

公开(公告)号：US20080285344A1

公开(公告)日：2008-11-20

申请号：US11749028

申请日：2007-05-15

Applicant: Eike Ruttkowski ,  Detlev Richter ,  Michael Specht ,  Joseph Willer ,  Dirk Manger ,  Kenny Oisin ,  Steffen Meyer ,  Klaus Knobloch ,  Holger Moeller ,  Doris Keitel Schulz ,  Jan Gutsche ,  Gert Koebernik ,  Christoph Friederich

Inventor： Eike Ruttkowski ,  Detlev Richter ,  Michael Specht ,  Joseph Willer ,  Dirk Manger ,  Kenny Oisin ,  Steffen Meyer ,  Klaus Knobloch ,  Holger Moeller ,  Doris Keitel Schulz ,  Jan Gutsche ,  Gert Koebernik ,  Christoph Friederich

IPC: G11C11/34 ,  H01L21/82

CPC classification number: H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Abstract translation: 本发明的实施例一般涉及集成电路，用于制造集成电路的方法，存储器模块和计算系统。