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    Dynamic latency map for memory optimization
    21.
    发明授权
    Dynamic latency map for memory optimization 有权
    用于内存优化的动态延迟图

    公开(公告)号：US07707379B2

    公开(公告)日：2010-04-27

    申请号：US11621182

    申请日：2007-01-09

    Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

    Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

    IPC: G06F12/00

    CPC classification number: G06F13/161 ,  G06F12/0802

    Abstract: In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a plurality of data units is determined. Upon each occurrence of a predefined event, a memory latency for each of the plurality of memory locations is determined. After the predefined event, a data unit with a high usage frequency is stored in a memory location with a low latency.

    Abstract translation: 在控制包括多个存储器位置的计算机可读存储器的方法中，确定多个数据单元的使用频率。 在每次发生预定事件时，确定多个存储器位置中的每一个的存储器等待时间。 在预定义的事件之后，具有高使用频率的数据单元被存储在具有低延迟的存储器位置中。

    Structure for Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data
    27.
    发明申请
    Structure for Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data 有权
    支持命令数据复制的高容量内存子系统的内存芯片结构

    公开(公告)号：US20090006798A1

    公开(公告)日：2009-01-01

    申请号：US12052831

    申请日：2008-03-21

    Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

    Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

    IPC: G06F12/00

    CPC classification number: G06F13/1684 ,  G06F12/084

    Abstract: A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining

    Abstract translation: 为包含用于接收数据访问命令的第一接口的存储器模块和用于将数据访问命令重新发送到其他存储器模块的第二接口提供设计结构，第二接口将接收到的数据访问命令的多个副本传播到多个其他存储器模块 。 存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。 优选地，存储器模块具有多模式操作，其中之一支持命令的多个复制，另一个支持传统的菊花链

    Structure for Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus
    28.
    发明申请
    Structure for Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus 有权
    用于支持多速总线的大容量存储器子系统的存储器芯片的结构

    公开(公告)号：US20090006781A1

    公开(公告)日：2009-01-01

    申请号：US12053131

    申请日：2008-03-21

    Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

    Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

    IPC: G06F12/00 ,  G06F1/06

    CPC classification number: G06F13/1689 ,  G06F13/1684

    Abstract: A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.

    Abstract translation: 为包含用于从外部源接收存储器访问命令的接口的存储器模块提供设计结构，其中接口的第一部分以第一总线频率接收存储器访问数据，并且接口的第二部分接收存储器访问数据 在第二个不同的总线频率。 优选地，存储器模块包含第二接口，用于重新传输也以双频操作的存储器访问数据。 存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。 优选地，存储器模块具有多模式操作，其中之一支持用于接收和重新传送数据访问命令的不同部分的双速总线，另一个支持常规的菊花链。

    Structure for Dual-Mode Memory Chip for High Capacity Memory Subsystem
    29.
    发明申请
    Structure for Dual-Mode Memory Chip for High Capacity Memory Subsystem 有权
    用于大容量存储器子系统的双模式存储器芯片的结构

    公开(公告)号：US20090006760A1

    公开(公告)日：2009-01-01

    申请号：US12053185

    申请日：2008-03-21

    Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

    Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

    IPC: G06F12/00

    CPC classification number: G06F12/0844 ,  G06F12/0607 ,  G06F12/0851

    Abstract: A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.

    Abstract translation: 提供了一种支持第一操作模式的双模式存储器芯片的设计结构，其中接收的数据访问命令包含芯片选择数据以识别由命令寻址的芯片，并且存储器芯片中的控制逻辑确定该命令是否被寻址到 芯片和第二操作模式，其中所接收的数据访问命令寻址一组多个芯片。 优选地，第一模式支持存储芯片的菊花链配置。 优选地，第二模式支持分层交错存储器子系统，其中每个可寻址的芯片集合被配置为树，命令和写入数据在树下传播，在树的每个后续级别增加的码片数量。

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