公开(公告)号：US08723021B2

公开(公告)日：2014-05-13

申请号：US13416354

申请日：2012-03-09

Applicant: Harold J. Hovel ,  Rainer K. Krause ,  Zhengwen Li ,  Huilong Zhu

Inventor： Harold J. Hovel ,  Rainer K. Krause ,  Zhengwen Li ,  Huilong Zhu

IPC: H01L31/032

CPC classification number: G02B1/113 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/1868 ,  Y02E10/547 ,  Y02P70/521

Abstract: A solar cell includes a substrate having an N-region and a P-region, a first anti-reflective layer disposed on the substrate, a metallic contact disposed on the first anti-reflective layer, a second anti-reflective layer disposed on the first anti-reflective layer and the metallic contact, and a region partially defined by the first anti-reflective layer and the second anti-reflective layer having diffused metallic contact material operative to form a conductive path to the substrate through the first anti-reflective layer, the metallic contact, and the second anti-reflective layer.

Abstract translation: 太阳能电池包括具有N区和P区的衬底，设置在衬底上的第一抗反射层，设置在第一抗反射层上的金属触点，设置在第一抗反射层上的第二抗反射层 抗反射层和金属接触，以及由第一抗反射层和第二抗反射层局部限定的区域，其具有扩散的金属接触材料，其可操作以通过第一抗反射层形成到衬底的导电路径， 金属触点和第二抗反射层。

公开(公告)号：US08710556B2

公开(公告)日：2014-04-29

申请号：US12937652

申请日：2010-06-25

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

IPC: H01L29/76 ,  H01L27/12 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

Abstract translation: 本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离 翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。 半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。

公开(公告)号：US08658507B2

公开(公告)日：2014-02-25

申请号：US12990714

申请日：2010-06-24

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qingqing Liang

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qingqing Liang

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/1054 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7848

Abstract: There is provided a MOSFET structure and a method of fabricating the same. The method includes: providing a semiconductor substrate; forming a dummy gate on the semiconductor substrate; forming source/drain regions; selectively etching the dummy gate to a position where a channel is to be formed; and epitaxially growing a channel layer at the position where the channel is to be formed and forming a gate on the channel layer, wherein the channel layer comprises a material of high mobility. Thereby, the channel of the device is replaced with the material of high mobility after the source/drain region is formed, and thus it is possible to suppress the short channel effect and also to improve the device performance.

Abstract translation: 提供了一种MOSFET结构及其制造方法。 该方法包括：提供半导体衬底; 在半导体衬底上形成虚拟栅极; 形成源/漏区; 选择性地将伪栅极蚀刻到要形成沟道的位置; 并且在通道的位置上外延生长沟道层，并在沟道层上形成栅极，其中沟道层包括高迁移率的材料。 因此，在形成源极/漏极区域之后，器件的沟道被高迁移率的材料代替，从而可以抑制短沟道效应并且还能够提高器件性能。

公开(公告)号：US08541280B2

公开(公告)日：2013-09-24

申请号：US13380654

申请日：2011-04-18

Applicant: Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: depositing an interlayer dielectric layer (105) on a semiconductor substrate (101) to cover a source/drain region (102) and a gate stack on the semiconductor substrate (101); etching the interlayer dielectric layer and the source/drain region, so as to form a contact hole (110) extending into the source/drain region; conformally forming an amorphous layer (111) on an exposed part of the source/drain region; forming a metal silicide layer (113) on a surface of the amorphous layer (111); and filling the contact hole (110) with a contact metal (114). Correspondingly, the present invention further provides a semiconductor structure. The present invention etches the source/drain region so that the exposed part comprises the bottom and a sidewall, thereby expanding the contact area between the contact metal in the contact hole and the source/drain region, and reducing the contact resistance. The present invention effectively eliminates EOR defects caused by the amorphous ion implantation by forming an amorphous substance by a selective deposition.

公开(公告)号：US20130221329A1

公开(公告)日：2013-08-29

申请号：US13582431

申请日：2012-03-29

Applicant: Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Zhi Jin ,  Xinyu Liu ,  Tianchun Ye

Inventor： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Zhi Jin ,  Xinyu Liu ,  Tianchun Ye

IPC: H01L29/66

CPC classification number: H01L29/66977 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/778

Abstract: An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc.

Abstract translation: 本发明的实施例公开了一种石墨烯装置，其包括多个石墨烯通道和一个浇口，其中所有石墨烯通道的一端连接到一个端子，所有的石墨烯通道与浇口接触并与门电连接， 石墨烯通道和栅极之间的角度是相互不同的。 由于不同石墨烯通道的不同的入射波角，每个石墨烯通道具有不同的隧道概率，每个石墨烯通道具有不同的导电条件，并且石墨烯装置可以用作诸如多路复用器或 解复用器等

公开(公告)号：US08507958B2

公开(公告)日：2013-08-13

申请号：US13112993

申请日：2011-05-20

Applicant: Haizhou Yin ,  Huilong Zhu ,  Zhijong Luo

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijong Luo

IPC: H01L29/772

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/823807 ,  H01L29/32 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.

Abstract translation: 晶体管及其形成方法技术领域本发明涉及晶体管及其形成方法。 本发明的晶体管包括半导体衬底; 形成在所述半导体衬底上的栅介电层; 形成在栅介质层上的栅极; 源极区和漏极区，位于所述半导体衬底中并在所述栅极的相应侧上，其中所述源极区和所述漏极区中的至少一个包括至少一个位错; 含有位于源区和漏区的硅的外延半导体层; 和外延半导体层上的金属硅化物层。

公开(公告)号：US20130200456A1

公开(公告)日：2013-08-08

申请号：US13696995

申请日：2011-11-29

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Huicai Zhong

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L27/12 ,  H01L21/743 ,  H01L21/762 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.

Abstract translation: 本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。 根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与 第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

公开(公告)号：US08492210B2

公开(公告)日：2013-07-23

申请号：US13144906

申请日：2011-02-25

Applicant: Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

Inventor： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC: H01L21/84

CPC classification number: H01L29/78648 ,  H01L21/8213 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66628

Abstract: The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced.

Abstract translation: 本发明涉及晶体管，包括晶体管的半导体器件和用于晶体管和半导体器件的制造方法。 根据本发明的晶体管包括：至少包括基层，第一半导体层，绝缘层和顺序层叠的第二半导体层的基板; 形成在所述第二半导体层上的栅叠层; 分别位于栅极堆叠的两侧的源极区域和漏极区域; 包括分别由所述绝缘层和所述第一半导体层形成的背栅电介质和背栅电极的背栅; 以及形成在背栅电极的一部分上的背栅极接触。 背栅极触点包括从背栅电极的表面凸起的外延部分，源区和漏区中的每一个包括从第二半导体层的表面凸出的外延部。 与常规晶体管相比，本发明的晶体管的制造工艺简化，制造成本降低。

公开(公告)号：US08492206B2

公开(公告)日：2013-07-23

申请号：US13375692

申请日：2011-08-29

Applicant: Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

Inventor： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

IPC: H01L21/335 ,  H01L21/70

CPC classification number: H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

Abstract: A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

Abstract translation: 公开了一种半导体器件结构及其制造方法。 在一个实施例中，所述方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

公开(公告)号：US08461650B2

公开(公告)日：2013-06-11

申请号：US13202221

申请日：2011-03-03

Applicant: Huilong Zhu ,  Hao Wu ,  Weiping Xiao

Inventor： Huilong Zhu ,  Hao Wu ,  Weiping Xiao

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78612

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device comprises a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor body located on the insulating layer; a cavity formed in the semiconductor body and into the insulating layer; source/drain regions abutting opposite first side faces of the semiconductor body; gates located on opposite second side faces of the semiconductor body; a channel layer interposed between the respective second side faces and the cavity; and a super-steep-retrograded-well and a halo super-steep-retrograded-well formed in the channel layer. The super-steep-retrograded-well and the halo super-steep-retrograded-well have opposite dopant polarities.

Abstract translation: 公开了半导体装置及其制造方法。 在一个实施例中，半导体器件包括半导体衬底; 位于所述半导体衬底上的绝缘层; 位于所述绝缘层上的半导体本体; 在半导体本体中形成并进入绝缘层的空腔; 源极/漏极区域邻接半导体本体的相对的第一侧面; 位于半导体本体的相对的第二侧面上的门; 插入在相应的第二侧面和空腔之间的沟道层; 并且在通道层中形成了一个超级陡峭的后退井和一个光晕超陡峭的回归井。 超级陡峭后退井和光晕超陡倾斜井具有相反的掺杂极性。