公开(公告)号：US09799750B2

公开(公告)日：2017-10-24

申请号：US13551107

申请日：2012-07-17

Applicant: Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

Inventor： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

IPC: H01L29/772 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

公开(公告)号：US08809918B2

公开(公告)日：2014-08-19

申请号：US13280094

申请日：2011-10-24

Applicant: Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

Inventor： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai

IPC: H01L29/76

CPC classification number: H01L21/26506 ,  H01L21/26593 ,  H01L21/76232 ,  H01L29/045 ,  H01L29/7833 ,  H01L29/7847

Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET.

Abstract translation: 一种方法包括形成金属氧化物半导体场效应晶体管（MOSFET），其包括形成与MOSFET的栅电极相邻的第一位错面，并形成与MOSFET的栅电极相邻的第二位错面。 第一和第二位错平面位于栅电极的同一侧，并延伸到MOSFET的源/漏区。

公开(公告)号：US08633070B2

公开(公告)日：2014-01-21

申请号：US12716100

申请日：2010-03-02

Applicant: Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

Inventor： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

IPC: H01L21/84

CPC classification number: H01L29/7833 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 该方法包括提供基底; 在衬底上形成栅极结构; 在由栅极结构插入的衬底的源极和漏极区域中形成外延层; 并且在形成外延层之后，在源极和漏极区域中形成轻掺杂的源极和漏极（LDD）特征。

公开(公告)号：US20130099314A1

公开(公告)日：2013-04-25

申请号：US13277872

申请日：2011-10-20

Applicant: Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

Inventor： Wei-Yuan Lu ,  Li-Ping Huang ,  Han-Ting Tsai ,  Wei-Ching Wang ,  Ming-Shuan Li ,  Hsueh-Jen Yang ,  Kuan-Chung Chen

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/324 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78654

Abstract: A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material.

Abstract translation: 公开了一种制造方法和具有多个位错结构的半导体器件。 示例性半导体器件包括覆盖半导体衬底的顶表面的栅极结构和设置在栅极结构的侧壁上且覆盖衬底顶表面的第一栅极间隔。 半导体器件还包括结晶半导体材料，其覆盖半导体衬底的顶表面并与第一栅极间隔物的侧壁相邻。 半导体器件还包括设置在第一栅极间隔物的侧壁上并覆盖结晶的半导体材料的第二栅极间隔物。 半导体器件还包括设置在半导体衬底中的第一应力区域和设置在半导体衬底和晶体化半导体材料中的第二应力区域。

公开(公告)号：US08368147B2

公开(公告)日：2013-02-05

申请号：US12761949

申请日：2010-04-16

Applicant: Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

Inventor： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC: H01L21/70

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

Abstract translation: 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。