公开(公告)号：US20090057745A1

公开(公告)日：2009-03-05

申请号：US12073398

申请日：2008-03-05

Applicant: Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

Inventor： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

IPC: H01L29/788 ,  H01L29/792 ,  H01L21/335

CPC classification number: H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203

Abstract: Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer.

Abstract translation: 示例性实施例提供了可以通过堆叠集成的非易失性存储器件，堆叠模块和制造非易失性存储器件的方法。 在根据示例性实施例的非易失性存储器件中，可以在衬底上形成至少一个底栅电极。 至少一个电荷存储层可以形成在至少一个底栅电极上，并且至少一个半导体沟道层可以形成在至少一个电荷存储层上。

公开(公告)号：US07479442B2

公开(公告)日：2009-01-20

申请号：US11071175

申请日：2005-03-04

Applicant: Takashi Noguchi ,  Wenxu Xianyu ,  Huaxiang Yin

Inventor： Takashi Noguchi ,  Wenxu Xianyu ,  Huaxiang Yin

IPC: H01L21/461

CPC classification number: H01L21/76254

Abstract: Provided is a method of manufacturing a single crystal Si film. The method includes: preparing a Si substrate on which a first oxide layer is formed and an insulating substrate on which a second oxide layer is formed; forming a dividing layer at a predetermined depth from a surface of the Si substrate by implanting hydrogen ions from above the first oxide layer; bonding the insulating substrate to the Si substrate so that the first oxide layer contacts the second oxide layer; and forming a single crystal Si film having a predetermined thickness on the insulating substrate by cutting the dividing layer by irradiating a laser beam from above the insulating substrate. Therefore, a single crystal Si film having a predetermined thickness can be formed on an insulating substrate.

Abstract translation: 提供制造单晶Si膜的方法。 该方法包括：制备其上形成有第一氧化物层的Si衬底和形成有第二氧化物层的绝缘衬底; 通过从所述第一氧化物层上方注入氢离子，从所述Si衬底的表面形成预定深度的分隔层; 将绝缘基板接合到Si衬底，使得第一氧化物层接触第二氧化物层; 以及通过从绝缘基板上方照射激光束切割分隔层，在绝缘基板上形成具有预定厚度的单晶硅膜。 因此，可以在绝缘基板上形成具有预定厚度的单晶Si膜。

公开(公告)号：US20080118754A1

公开(公告)日：2008-05-22

申请号：US11976009

申请日：2007-10-19

Applicant: Wenxu Xianyu ,  Young-soo Park ,  Hans S. Cho ,  Huaxiang Yin ,  Hyuck Lim

Inventor： Wenxu Xianyu ,  Young-soo Park ,  Hans S. Cho ,  Huaxiang Yin ,  Hyuck Lim

IPC: C30B13/06 ,  B32B9/00

CPC classification number: C30B29/06 ,  C30B13/24 ,  C30B25/02 ,  C30B29/60 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02675 ,  H01L29/42392 ,  H01L29/78696 ,  Y10T428/2962

Abstract: A method of fabricating a single crystal silicon rod may include forming an insulation layer on a substrate, forming a hole in the insulation layer, selectively growing silicon in the hole, forming a silicon layer on the hole and on the insulation layer, forming a rod pattern on the silicon layer in a direction that is non-radial with respect to the hole, and melting the silicon layer and crystallizing the silicon layer by illuminating a laser beam on the silicon layer where the rod pattern is formed to generate a nucleation site at a position corresponding to the hole. According to the method, a single crystal silicon rod having no defects may be formed.

Abstract translation: 制造单晶硅棒的方法可以包括在衬底上形成绝缘层，在绝缘层中形成孔，选择性地生长孔中的硅，在孔和绝缘层上形成硅层，形成棒 在相对于孔的非径向的方向上在硅层上形成图案，并且通过照射形成棒图案的硅层上的激光束来熔化硅层并使硅层结晶，从而在硅层上产生成核位置 对应于孔的位置。 根据该方法，可以形成没有缺陷的单晶硅棒。

公开(公告)号：US20070287232A1

公开(公告)日：2007-12-13

申请号：US11760043

申请日：2007-06-08

Applicant: Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Hans S. CHO ,  Huaxiang YIN

Inventor： Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Hans S. CHO ,  Huaxiang YIN

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/66765 ,  H01L21/02532 ,  H01L21/02686 ,  H01L27/1281

Abstract: A method of manufacturing a bottom gate thin film transistor (“TFT”), in which a polycrystalline channel region having a large grain size is formed relatively simply and easily, includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the gate electrode, forming an amorphous semiconductor layer on the gate insulating layer, patterning the amorphous semiconductor layer to form an amorphous channel region on the gate electrode, melting the amorphous channel region using a laser annealing method to form a melted amorphous channel region, and crystallizing the melted amorphous channel region to form a laterally grown polycrystalline channel region.

Abstract translation: 相对简单且容易地形成具有大晶粒尺寸的多晶硅沟道区的底栅薄膜晶体管（“TFT”）的制造方法包括：在基板上形成栅极绝缘层，形成栅极绝缘层 所述基板覆盖所述栅极电极，在所述栅极绝缘层上形成非晶半导体层，图案化所述非晶半导体层以在所述栅电极上形成非晶态沟道区域，使用激光退火方法熔化所述非晶态沟道区域以形成熔融无定形 并使熔融的无定形沟道区域结晶，形成横向生长的多晶沟道区域。

公开(公告)号：US20070187668A1

公开(公告)日：2007-08-16

申请号：US11598040

申请日：2006-11-13

Applicant: Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Huaxiang Yin

Inventor： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Huaxiang Yin

IPC: H01L31/00 ,  C30B13/02 ,  C30B19/00 ,  H01L29/04

CPC classification number: C30B25/18 ,  C30B23/025 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02675 ,  H01L21/30625

Abstract: A single crystal substrate and method of fabricating the same are provided. The single crystal substrate includes an insulator having a window exposing a portion of a substrate, a selective epitaxial growth layer formed on the portion of the substrate exposed through the window and a single crystalline layer formed on the insulator and the selective epitaxial growth layer using the selective epitaxial growth layer as an epitaxial seed layer.

Abstract translation: 提供单晶基板及其制造方法。 单晶衬底包括具有暴露衬底的一部分的窗口的绝缘体，形成在通过窗口暴露的衬底的部分上的选择性外延生长层和在绝缘体上形成的单晶层和使用所述选择性外延生长层 选择性外延生长层作为外延种子层。

公开(公告)号：US20060292313A1

公开(公告)日：2006-12-28

申请号：US11473067

申请日：2006-06-23

Applicant: Wenxu Xianyu ,  Hans Cho ,  Takashi Noguchi ,  Young-Soo Park ,  Xiaoxin Zhang ,  Huaxiang Yin ,  Hyuck Lim ,  Kyung-Bae Park ,  Suk-Pil Kim

Inventor： Wenxu Xianyu ,  Hans Cho ,  Takashi Noguchi ,  Young-Soo Park ,  Xiaoxin Zhang ,  Huaxiang Yin ,  Hyuck Lim ,  Kyung-Bae Park ,  Suk-Pil Kim

IPC: C09K19/00

CPC classification number: C30B29/06 ,  Y10T428/10

Abstract: Provided are methods of forming a more highly-oriented silicon thin layer having a larger grain size, and a substrate having the same. The methods may include forming an aluminum (Al) layer on a base substrate, forming a more highly-oriented Al layer by recrystallizing the Al layer under vacuum, forming a more highly-oriented γ-Al2O3 layer on the more highly-oriented Al layer and/or epitaxially growing a silicon layer on the more highly-oriented γ-Al2O3 layer. The method may be used to manufacture a semiconductor device having higher carrier mobility.

Abstract translation: 提供了形成具有较大晶粒尺寸的更高取向硅薄层的方法以及具有其的基板。 所述方法可以包括在基底基板上形成铝（Al）层，通过在真空下重结晶Al层，形成更高取向的Al层，形成更高取向的γ-Al 2 O 在更高取向的Al层上和/或在更高取向的γ-Al 2 O 3上外延生长硅层3层 >层。 该方法可用于制造具有较高载流子迁移率的半导体器件。

公开(公告)号：US20060267100A1

公开(公告)日：2006-11-30

申请号：US11430117

申请日：2006-05-09

Applicant: Takashi Noguchi ,  Hans Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaozin Zhang

Inventor： Takashi Noguchi ,  Hans Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaozin Zhang

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  Y10S257/903

Abstract: A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of . The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.

Abstract translation: 包括基板，形成在基板上的P-MOS单晶TFT的半导体器件和形成在P-MOS单晶TFT上的N-MOS单晶TFT。 P-MOS单晶TFT的源极区域和N-MOS单晶TFT的源极区域可以彼此连接。 P-MOS单晶TFT和N-MOS单晶TFT可以共用公共栅极。 此外，P-MOS单晶TFT可以包括具有（100）的晶面和<100>的晶体方向的单晶硅层。 N-MOS单晶TFT可以包括与P-MOS单晶TFT的单晶硅层相同的晶体方向的单晶硅层，其拉应力大于P-MOS的单晶硅层 单晶TFT。

公开(公告)号：US09548387B2

公开(公告)日：2017-01-17

申请号：US13812941

申请日：2012-08-27

Applicant: Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7845 ,  H01L29/785

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

Abstract translation: 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

公开(公告)号：US20150295068A1

公开(公告)日：2015-10-15

申请号：US14436892

申请日：2012-10-30

Applicant: Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

Inventor： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

Abstract: Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

Abstract translation: 提供一种用于制造MOSFET的方法，包括：在半导体衬底中形成浅沟槽隔离（STI）以限定MOSFET的有源区; 以STI作为掩模进行蚀刻，露出半导体衬底的表面，并且相对于半导体衬底的表面突出STI的一部分，导致突出部分; 在所述突出部分的侧壁上形成第一间隔件; 在半导体衬底上形成栅叠层; 形成围绕所述栅极叠层的第二间隔物; 用STI，栅极叠层，第一间隔物和第二间隔物作为掩模在半导体衬底中形成开口; 外延生长具有每个开口的底表面和侧壁的半导体层作为生长种子层; 并且对半导体层进行离子注入以形成源区和漏区。

公开(公告)号：US08921171B2

公开(公告)日：2014-12-30

申请号：US13699734

申请日：2012-07-24

Applicant: Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

Inventor： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8238 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.

Abstract translation: 一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在 底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。