Abstract:
A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.
Abstract:
A content management method in an intelligent robot service system includes: generating a key to distribute the key to a content generation node and a content execution node; generating a signature for a content using the distributed key in the content generation node; providing the content and the signature to the content execution node; and verifying a validity of the content in the content execution node to execute the verified content.
Abstract:
A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell.
Abstract:
A capacitive sensor includes an upper electrode layer having a plurality of electrodes disposed in line with each other, a lower electrode layer having a plurality of electrodes disposed in line with each other, an insulating layer disposed between the upper electrode layer and the lower electrode layer, and a layer of bumps made of insulating material formed above the area where the electrodes of the upper electrode layer and the electrodes of the lower electrode later are crossed. The sensor detects the proximity of approaching objects by the capacitance change between the electrodes disposed in the upper electrode layer, and detects the contact of any objects by the capacitance change between the electrodes of the upper electrode layer and the electrodes of the lower electrode layer.
Abstract:
A device authentication method and device authentication apparatus in a multi domain home network environment are provided. The method includes registering a new device in each local domain and issuing a local domain certificate; making an agreement between local domains in order to authenticate a device registered to another local domain; when the device registered to the home local domain or another local domain requests a service, authenticating the device via communication inside the local domains, thereby minimizing a user's intervention, making it easier to use the apparatus, reducing a device operation with regard to a device having limited performance, and making it easier to extend the apparatus.
Abstract:
Example embodiments relate to a manufacturing device of an anti-reflecting structure and a method for manufacturing the anti-reflecting structure. The manufacturing device of an anti-reflecting structure includes a carrier film on which a stamp structure is formed, an unwinding unit which unwinds the carrier film, a substrate support unit which provides a target substrate to the carrier film, a pressing unit which applies pressure to the carrier film so that a resin provided in the stamp structure is provided to the target substrate, and a winding unit which winds the carrier film from which an anti-reflecting pattern is transferred to the target substrate, wherein the pressing unit includes a chamber which stores the target substrate, and a vent hole formed in the chamber, and air within the chamber is discharged through the vent hole to lower the air pressure in the chamber and apply pressure to the carrier film.
Abstract:
The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
Abstract:
A safe operation apparatus for a moving object includes: a distraction detection unit for detecting distraction information of a user operating a moving object; a controller for collecting the distraction information from the distraction detection unit, calculating a user's distraction state value, and controlling the moving object to be automatically operated or warning of the distraction state based on the distraction state value; and an automatic operation unit for automatically operating the moving object under the control of the controller. The apparatus further includes a communication unit for transmitting the user's distraction state to a remote control center or an adjacent different moving object under the control of the controller.
Abstract:
Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.
Abstract:
Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.