公开(公告)号：US20120231596A1

公开(公告)日：2012-09-13

申请号：US13479121

申请日：2012-05-23

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L21/335

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US08264004B2

公开(公告)日：2012-09-11

申请号：US12715034

申请日：2010-03-01

Applicant: Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

Inventor： Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L29/778

CPC classification number: H01L29/161 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/7782 ,  H01L29/78

Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.

Abstract translation: 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。

公开(公告)号：US20120199813A1

公开(公告)日：2012-08-09

申请号：US13450359

申请日：2012-04-18

Applicant: Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Majumdar Amian ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Majumdar Amian ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract translation: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

公开(公告)号：US08237153B2

公开(公告)日：2012-08-07

申请号：US13046061

申请日：2011-03-11

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。

公开(公告)号：US08211772B2

公开(公告)日：2012-07-03

申请号：US12646427

申请日：2009-12-23

Applicant: Jack T. Kavalieros ,  Nancy M. Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

Inventor： Jack T. Kavalieros ,  Nancy M. Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

Abstract translation: 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

公开(公告)号：US20120153387A1

公开(公告)日：2012-06-21

申请号：US12975278

申请日：2010-12-21

Applicant: Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

Inventor： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract translation: 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。

公开(公告)号：US20110156006A1

公开(公告)日：2011-06-30

申请号：US13046061

申请日：2011-03-11

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。

公开(公告)号：US20110147811A1

公开(公告)日：2011-06-23

申请号：US12646427

申请日：2009-12-23

Applicant: Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

Inventor： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

Abstract translation: 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

公开(公告)号：US07888221B2

公开(公告)日：2011-02-15

申请号：US12229459

申请日：2008-08-22

Applicant: Jack T. Kavalieros ,  Matthew V. Metz ,  Gilbert Dewey ,  Been-Yih Jin ,  Justin K. Brask ,  Suman Datta ,  Robert S. Chau

Inventor： Jack T. Kavalieros ,  Matthew V. Metz ,  Gilbert Dewey ,  Been-Yih Jin ,  Justin K. Brask ,  Suman Datta ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/7391

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract translation: 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。

公开(公告)号：US07879739B2

公开(公告)日：2011-02-01

申请号：US11382428

申请日：2006-05-09

Applicant: Willy Rachmady ,  James Blackwell ,  Suman Datta ,  Jack T. Kavalieros ,  Mantu K. Hudait

Inventor： Willy Rachmady ,  James Blackwell ,  Suman Datta ,  Jack T. Kavalieros ,  Mantu K. Hudait

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/31616 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28264 ,  H01L29/513 ,  H01L29/78

Abstract: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.

Abstract translation: 本发明的实施例提供了在基板和高k电介质层之间基本上不具有III-V族衬底的氧化物的III-V族衬底上形成高k电介质层的方法。 氧化物可以从衬底去除。 有机金属化合物可以在去除氧化物的基底上形成覆盖层。 然后可以形成高k电介质层，导致衬底和高k电介质层之间的薄过渡层，并且在衬底和高k电介质层之间基本上不存在III-V族衬底的氧化物。