公开(公告)号：US07839645B2

公开(公告)日：2010-11-23

申请号：US12606136

申请日：2009-10-26

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first surface and a first plurality of circuits coupled to the first surface. The first plurality of circuits is in electrical communication with the electrical contacts. The module further includes a second surface and a second plurality of circuits coupled to the second surface. The second plurality of circuits is in electrical communication with the electrical contacts. The second surface faces the first surface. The module further includes at least one thermally conductive layer positioned between the first surface and the second surface. The at least one thermally conductive layer is in thermal communication with the first plurality of circuits, the second plurality of circuits, and a first set of the plurality of electrical contacts.

Abstract translation: 模块可电连接到计算机系统。 模块包括可电连接到计算机系统的多个电触点。 模块还包括耦合到第一表面的第一表面和第一多个电路。 第一组多个电路与电触点电连通。 模块还包括耦合到第二表面的第二表面和第二多个电路。 第二组电路与电触点电连通。 第二表面面向第一表面。 模块还包括位于第一表面和第二表面之间的至少一个导热层。 所述至少一个导热层与所述第一多个电路，所述第二多个电路和所述多个电触头的第一组热连通。

公开(公告)号：US07811097B1

公开(公告)日：2010-10-12

申请号：US12237162

申请日：2008-09-24

Applicant: Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

Inventor： Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

IPC: H01R12/00

CPC classification number: H05K1/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/4691 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: A circuit includes a first plurality of contacts configured to be in electrical communication with a plurality of electronic devices. The circuit card further includes a flexible portion including a dielectric layer, a second plurality of contacts, and a plurality of electrical conduits extending across a region of the flexible portion and in electrical communication with one or more contacts of the first plurality of contacts and with the second plurality of contacts. The flexible portion further includes an electrically conductive layer extending across the region of the flexible portion. The electrically conductive layer is superposed with the plurality of electrical conduits with the dielectric layer therebetween. The electrically conductive layer does not overlay one or more portions of the dielectric layer in the region of the flexible portion.

Abstract translation: 电路包括构造成与多个电子设备电连通的第一多个触点。 电路卡还包括柔性部分，该柔性部分包括电介质层，第二多个触点以及跨越柔性部分的区域延伸并且与第一多个触点的一个或多个触点电连通并且与 第二个多个联系人。 柔性部分还包括延伸穿过柔性部分的区域的导电层。 导电层与多个电导管重叠，其间具有介电层。 在柔性部分的区域中，导电层不覆盖电介质层的一个或多个部分。

公开(公告)号：US20090201711A1

公开(公告)日：2009-08-13

申请号：US12408652

申请日：2009-03-20

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C5/02

CPC classification number: G11C5/04 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02D10/13 ,  Y02P70/611

Abstract: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.

Abstract translation: 存储器模块包括多个存储器件和电路。 每个存储器件具有相应的负载。 电路电耦合到多个存储器件并被配置为电耦合到计算机系统的存储器控​​制器。 该电路选择性地将存储器件的一个或多个负载与计算机系统隔离。 该电路包括在计算机系统的系统存储器域和存储器模块的物理存储器域之间转换的逻辑。

公开(公告)号：US06751113B2

公开(公告)日：2004-06-15

申请号：US10094512

申请日：2002-03-07

Applicant: Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

Inventor： Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

IPC: G11C506

CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

公开(公告)号：US08756364B1

公开(公告)日：2014-06-17

申请号：US13287042

申请日：2011-11-01

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G06F12/00

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 存储器模块具有至少部分地针对第一数量的芯片选择信号而激活的第一数量的双数据速率（DDR）存储器设备。 电路可配置为从计算机系统接收地址信号和第二数量的芯片选择信号。 该电路还可配置为产生并将锁相时钟信号发送到第一数量的等级，并且至少部分地响应于锁相时钟信号，地址信号， 和第二数量的芯片选择信号。

公开(公告)号：US08516188B1

公开(公告)日：2013-08-20

申请号：US13287081

申请日：2011-11-01

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F13/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals smaller than the first number of chip-select signals. The circuit is further configurable to generate phase-locked clock signals, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Abstract translation: 电路被配置为安装在被配置为可操作地耦合到计算机系统的存储器模块上。 存储器模块具有由第一数量的芯片选择信号激活的第一数量的双数据速率（DDR）存储器电路。 电路可配置为接收包括地址信号和小于第一数量的芯片选择信号的第二数量的芯片选择信号的信号。 该电路还可配置成产生锁相时钟信号，以至少部分地响应于该组信号来选择性地隔离来自计算机系统的第一数量级别的至少一级的负载，并且产生第一 芯片选择信号的数量至少部分地响应于锁相时钟信号，地址信号和第二数量的芯片选择信号。

公开(公告)号：US08516185B2

公开(公告)日：2013-08-20

申请号：US12761179

申请日：2010-04-15

Applicant: Hyun Lee ,  Jayesh R. Bhakta

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

Abstract translation: 提供了利用一个或多个存储器模块的存储器系统和方法。 存储器模块包括多个存储器件和被配置为从系统存储器控制器接收控制信息并产生模块控制信号的控制器。 存储器模块还包括多个电路，例如逐字节缓冲器，其配置为将多个存储器设备与系统存储器控制器选择性地隔离。 响应于模块控制信号，这些电路可操作地将写数据从系统存储器控制器驱动到多个存储器装置，并将来自多个存储器件的读取数据合并到系统存储器控制器。 电路分布在彼此分开的相应位置。

公开(公告)号：US20120250386A1

公开(公告)日：2012-10-04

申请号：US13412243

申请日：2012-03-05

Applicant: Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

IPC: G11C5/02

CPC classification number: G06F13/1684 ,  G06F13/4027 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  H05K1/0216 ,  H05K1/0243 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Abstract translation: 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控​​制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。

公开(公告)号：US20120239874A1

公开(公告)日：2012-09-20

申请号：US13411344

申请日：2012-03-02

Applicant: Hyun Lee ,  Jayesh R. Bhakta ,  Paresh Sheth

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Paresh Sheth

IPC: G06F12/00

CPC classification number: G06F13/161 ,  G06F13/1673

Abstract: Systems and methods are described for resolving certain interoperability issues among multiple types of memory modules in the same memory subsystem. The system provides a single data load DIMM for constructing a high density and high speed memory subsystem that supports the standard JEDEC RDIMM interface while presenting a single load to the memory controller. At least one memory module includes one or more DRAM, a bi-directional data buffer and an interface bridge with a conflict resolution block. The interface bridge translates the CAS latency (CL) programming value that a memory controller sends to program the DRAMs, modifies the latency value, and is used for resolving command conflicts between the DRAMs and the memory controller to insure proper operation of the memory subsystem.

Abstract translation: 描述了系统和方法，用于解决同一内存子系统中多种类型的内存模块之间的某些互操作性问题。 该系统提供单个数据加载DIMM，用于构建高密度和高速存储器子系统，支持标准JEDEC RDIMM接口，同时向存储器控制器提供单个负载。 至少一个存储器模块包括一个或多个DRAM，双向数据缓冲器和具有冲突解决块的接口桥。 接口桥转换存储器控制器向DRAM编程的CAS延迟（CL）编程值，修改延迟值，并用于解决DRAM和存储器控制器之间的命令冲突，以确保存储器子系统的正确操作。

公开(公告)号：US08154901B1

公开(公告)日：2012-04-10

申请号：US12422853

申请日：2009-04-13

Applicant: Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

IPC: G11C5/02

CPC classification number: G06F13/1684 ,  G06F13/4027 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  H05K1/0216 ,  H05K1/0243 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Abstract translation: 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控​​制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。