Abstract:
A lowermost layer of control chips carries on it layers of memory chips. The memory chips are contacted via looped-through contacts that reach from one side of the other side of the memory chips and they are driven by the control chips that contain the test circuit for the memory chips.
Abstract:
A correction method in which characteristic curves and/or correction values are produced, by way of which the drive current for one or more electrically activated hydraulic values operated in an analog fashion is measured during a pressure regulation in such a way that, during the operation of an anti-lock regulation, one or a respective characteristic curve is first prescribed and then the prescribed characteristic curve is corrected, particularly in a learning process, wherein, after a pressure build-up phase, the current pressure model value (Pmod) is compared to and/or analyzed using a model locking pressure level (Pmax).
Abstract:
An actuator for a speed governor of an elevator system includes a governor wheel equipped with at least two flyweights. The governor wheel can be driven by a governor cable looped around it. An actuator wheel is stationary in a basic position. A coupler engages the actuator wheel when the governor wheel attains an actuation speed and thus couples with the governor wheel so that the actuator wheel is caused to rotate. An elastic material, preferably transmitting a high degree of friction, is provided between the coupler and the actuator wheel. The actuator wheel has a lining or tire of the elastic material and/or the coupler is equipped with the elastic material.
Abstract:
A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.
Abstract:
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
Abstract:
An integrated semiconductor circuit, in particular a semiconductor memory configuration, which can be operated in various operating modes and which has an apparatus for switching between these operating modes is described. The semiconductor circuit has a switching apparatus with at least one fuse unit, which can be blown and programmed from the exterior.
Abstract:
An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.
Abstract:
The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connection of the contact (11a′).
Abstract:
An actuator for a speed governor of an elevator system includes a governor wheel equipped with at least two flyweights. The governor wheel can be driven by a governor cable looped around it. An actuator wheel is stationary in a basic position. A coupler engages the actuator wheel when the governor wheel attains an actuation speed and thus couples with the governor wheel so that the actuator wheel is caused to rotate. An elastic material, preferably transmitting a high degree of friction, is provided between the coupler and the actuator wheel. The actuator wheel has a lining or tyre of the elastic material and/or the coupler is equipped with the elastic material.
Abstract:
According to one general aspect, a method for managing a plurality of different tenants on a shared computing infrastructure including at least one application server apparatus may include associating a tenant with a plurality of services, wherein each service provides a set of actions that the service is configured to perform. In some embodiments, the method may include associating at least one tenant runlevel for each associated service with the tenant. In various embodiments, the method may include, when the application server apparatus executes a service for the tenant, determining the tenant runlevel associated with the tenant, and managing the set of actions configured to be performed by the service based at least in part upon the tenant runlevel associated with the tenant and the service.