Substrate bias voltage generator and method of generating substrate bias voltage
    21.
    发明申请
    Substrate bias voltage generator and method of generating substrate bias voltage 失效
    衬底偏置电压发生器和产生衬底偏置电压的方法

    公开(公告)号:US20070153611A1

    公开(公告)日:2007-07-05

    申请号:US11602347

    申请日:2006-11-21

    Applicant: Jong Won Lee

    Inventor: Jong Won Lee

    CPC classification number: G11C5/146 G05F3/205

    Abstract: A substrate bias voltage detection unit compares a level of a substrate bias voltage with a reference voltage in response to a self-refresh signal, an idle signal, and a refresh count signal so as to output an oscillating driving signal, enables the oscillating driving signal when the substrate bias voltage is equal to or higher than a first level in a normal mode, disables the oscillating driving signal when the substrate bias voltage is at a second level in a self-refresh mode, and disables the oscillating driving signal when the substrate bias voltage is at a third level in the self-refresh mode. An oscillation unit outputs an oscillating signal according to the oscillating driving signal. A voltage pumping unit controls pumping of the substrate bias voltage according to an output signal of the oscillation unit and then outputs a pumped substrate bias voltage.

    Abstract translation: 衬底偏置电压检测单元响应于自刷新信号,空闲信号和刷新计数信号将衬底偏置电压的电平与参考电压进行比较以输出振荡驱动信号,使振荡驱动信号 当基板偏置电压在正常模式下等于或高于第一电平时,当自刷新模式中衬底偏置电压处于第二电平时禁用振荡驱动信号,并且当衬底偏置电压处于第二电平时禁用振荡驱动信号 自刷新模式下的偏置电压处于第三级。 振荡单元根据振荡驱动信号输出振荡信号。 电压抽取单元根据振荡单元的输出信号控制衬底偏置电压的泵浦,然后输出泵浦的衬底偏置电压。

    Multilevel phase change memory
    25.
    发明申请

    公开(公告)号:US20060249725A1

    公开(公告)日:2006-11-09

    申请号:US11122363

    申请日:2005-05-05

    Applicant: Jong-Won Lee

    Inventor: Jong-Won Lee

    Abstract: A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other. This means that a higher current is necessary to convert the material that has the largest cross-sectional area. As a result, different current levels may be utilized to convert different amounts of the chalcogenide material to the amorphous or reset state. A distinguishable resistance may be associated with each of those different amounts of amorphous material, providing the opportunity to engineer a number of different current selectable programmable states.

    Anti-fuse circuit for improving reliability and anti-fusing method using the same
    26.
    发明申请
    Anti-fuse circuit for improving reliability and anti-fusing method using the same 审中-公开
    用于提高可靠性的抗熔丝电路和使用其的抗熔融方法

    公开(公告)号:US20060214261A1

    公开(公告)日:2006-09-28

    申请号:US11322148

    申请日:2005-12-29

    CPC classification number: G11C17/16 H01L23/5252 H01L2924/0002 H01L2924/00

    Abstract: An anti-fuse circuit includes an anti-fuse device and an electric field control unit. The anti-fuse device is formed having a MOS structure including a first junction, a second junction and a gate terminal. The electric field control unit performs a control operation so that an electric field is formed in the anti-fuse device at the time of an anti-fusing operation. Electric fields formed at the first and second junctions of the anti-fuse device are separately controlled, so that breakdown can occur at two points. Further, the gate terminal of the anti-fuse device is implemented in the form of a band-shaped closed circuit.

    Abstract translation: 反熔丝电路包括反熔丝器件和电场控制单元。 反熔丝器件形成为具有包括第一结,第二结和栅极端的MOS结构。 电场控制单元执行控制操作,使得在防融熔操作时在反熔丝装置中形成电场。 形成在反熔丝器件的第一和第二结的电场被单独控制,从而可以在两点发生击穿。 此外,反熔丝器件的栅极端子以带状闭合电路的形式实现。

    Mold apparatus
    27.
    发明申请
    Mold apparatus 有权
    模具设备

    公开(公告)号:US20050276875A1

    公开(公告)日:2005-12-15

    申请号:US11142232

    申请日:2005-06-02

    Applicant: Jong-won Lee

    Inventor: Jong-won Lee

    Abstract: A mold apparatus having at least a pair of molds formed with a cavity, at least one pipe accommodator formed in the molds, at least one heat pipe mounted in the pipe accommodator, a heat-cool source part connected to the heat pipe the heat and cool the heat pipe, and a controller to control the heat-cool source part to selectively heat and cool the heat pipe. Thus a mold apparatus to reduce a molding cycle and improve the quality of a molded product's appearance is provided.

    Abstract translation: 一种模具装置,具有形成有空腔的至少一对模具,形成在模具中的至少一个管容纳器,安装在管容纳器中的至少一个热管,连接到热管的热源部分, 冷却热管,控制器控制热源部分选择性地加热和冷却热管。 因此,提供了减少成型周期并提高模制品外观质量的模具装置。

    Chemical/mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same
    28.
    发明授权
    Chemical/mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same 失效
    化学/机械抛光浆料和化学机械抛光工艺以及采用其的浅沟槽隔离工艺

    公开(公告)号:US06914001B2

    公开(公告)日:2005-07-05

    申请号:US10351539

    申请日:2003-01-27

    CPC classification number: H01L21/31053 C09G1/02 C09K3/1463

    Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.

    Abstract translation: CMP氧化物浆料包括含有磨料颗粒和两种或更多种不同钝化剂的水溶液。 优选地,水溶液由去离子水组成,磨料颗粒是选自二氧化铈,二氧化硅,氧化铝,二氧化钛,氧化锆和氧化锗的金属氧化物。 此外,第一钝化剂可以是阴离子,阳离子或非离子表面活性剂,第二钝化剂可以是邻苯二甲酸及其盐。 在一个实例中,第一钝化剂是聚乙烯基磺酸,第二钝化剂是邻苯二甲酸氢钾。 该浆料表现出高的氧化物与氮化硅的去除选择性。

    Polishing pad conditioner and chemical mechanical polishing apparatus having the same
    29.
    发明申请
    Polishing pad conditioner and chemical mechanical polishing apparatus having the same 有权
    抛光垫调节剂及其化学机械抛光装置

    公开(公告)号:US20050113009A1

    公开(公告)日:2005-05-26

    申请号:US10985206

    申请日:2004-11-10

    CPC classification number: B24B53/017 B24B53/02

    Abstract: Chemical mechanical apparatuses including a polishing pad conditioning unit for improving a conditioning rate and wear uniformity of a polishing pad are provided. In one aspect, a chemical mechanical polishing apparatus includes a polishing pad conditioner including conditioning disks disposed in a radial direction of a planarizing surface of a circular polishing pad and contacted with the planarizing surface of the circular polishing pad during rotation of the circular polishing pad. The conditioning disks are connected to first drive units supported by an arm disposed over the circular polishing pad and extended in a radial direction of a planarizing surface of the circular polishing pad. The arm is connected to second drive units. The second drive units move the arm horizontally and reciprocally in the radial direction of the planarizing surface of the circular polishing pad. Thus, a conditioning rate and wear uniformity of the polishing pad may be improved.

    Abstract translation: 提供了包括用于改善抛光垫的调理率和磨损均匀性的抛光垫调节单元的化学机械设备。 在一个方面,一种化学机械抛光装置包括抛光垫调节器,其包括在圆形抛光垫的平坦化表面的径向方向上设置的调节盘,并且在圆形抛光垫的旋转期间与圆形抛光垫的平坦化表面接触。 调节盘连接到由设置在圆形抛光垫上的臂支撑的第一驱动单元,并且在圆形抛光垫的平坦化表面的径向方向上延伸。 臂连接到第二个驱动单元。 第二驱动单元在圆形抛光垫的平坦化表面的径向水平和往复地移动臂。 因此,可以提高抛光垫的调理率和磨损均匀性。

    Method of forming metal pattern using selective electroplating process
    30.
    发明申请
    Method of forming metal pattern using selective electroplating process 审中-公开
    使用选择性电镀工艺形成金属图案的方法

    公开(公告)号:US20050070090A1

    公开(公告)日:2005-03-31

    申请号:US10875434

    申请日:2004-06-24

    Abstract: A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the blanket region. A polishing/plating stop layer and an upper seed layer are conformally formed on the diffusion barrier layer in a successive manner. The polishing/plating layer in the blanket region is exposed by selectively removing the upper seed layer in the blanket region, and, at the same time, a seed layer pattern remaining in the trenches is formed. An upper conductive layer is formed to fill the trench surrounded by the seed layer pattern using an electroplating process. Then, the dielectric layer in the blanket region is exposed by planarizing the upper conductive layer, the polishing/plating stop layer, the seed layer pattern, and the diffusion barrier layer.

    Abstract translation: 提供了使用选择性电镀工艺形成金属图案的方法。 首先,在下层形成介电层。 然后,通过图案化介电层形成限定覆盖区域的沟槽。 扩散阻挡层在沟槽和覆盖区域中共形地形成。 抛光/电镀停止层和上部种子层以连续的方式共形地形成在扩散阻挡层上。 通过选择性地去除覆盖区域中的上部种子层,暴露覆盖区域中的抛光/镀覆层,并且同时形成留在沟槽中的晶种层图案。 形成上导电层以使用电镀工艺填充由种子层图案包围的沟槽。 然后,通过平坦化上导电层,抛光/电镀停止层,种子层图案和扩散阻挡层来曝光覆盖区域中的电介质层。

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