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    Managing Shared Resources Between Multiple Processing Devices
    23.
    发明申请
    Managing Shared Resources Between Multiple Processing Devices 有权
    管理多个处理设备之间的共享资源

    公开(公告)号：US20150186313A1

    公开(公告)日：2015-07-02

    申请号：US14141828

    申请日：2013-12-27

    Applicant: Inder M. Sodhi ,  Joydeep Ray ,  Varghese George

    Inventor： Inder M. Sodhi ,  Joydeep Ray ,  Varghese George

    IPC: G06F13/36 ,  G06F9/50

    CPC classification number: G06F13/36 ,  G06F9/52

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.

    Abstract translation: 根据本文公开的实施例，提供了用于管理多个处理设备之间的共享资源的系统和方法。 处理器可以包括包括包括非相干数据的第一非相干硬件块（hb）的第一处理设备和包括包括非相干数据的第二非相干hb的第二处理设备。 处理器还可以包括与第一非相干hb和第二非相干hb通信的第一hb以跟踪和共享第一和第二处理设备之间的非相干数据。

    Writeback mechanisms for improving far memory utilization in multi-level memory architectures
    25.
    发明授权
    Writeback mechanisms for improving far memory utilization in multi-level memory architectures 有权
    用于改善多级内存架构中远程内存利用率的回写机制

    公开(公告)号：US09032099B1

    公开(公告)日：2015-05-12

    申请号：US14104260

    申请日：2013-12-12

    Applicant: Jorge E. Parra ,  Marc Torrant ,  Joydeep Ray

    Inventor： Jorge E. Parra ,  Marc Torrant ,  Joydeep Ray

    IPC: G06F3/06 ,  G06F12/08 ,  G06F13/38 ,  G06F5/00

    CPC classification number: G06F12/0804 ,  G06F12/08 ,  Y02D10/13

    Abstract: Multi-level memory architecture technologies are described. One processor includes a requesting unit, a first memory interface to couple to a far memory (FM), a second memory interface to couple to a near memory (NM) and a multi-level memory controller (MLMC) coupled to the requesting unit, the first memory interface and the second memory interface. The MLMC is to write data into a memory page of NM in response to a request from the requesting unit to retrieve the memory page from FM. The MLMC receives a hint from the requesting unit and clears a writeback bit for the memory page indicated in the hint. The hint indicates that the data contained in the memory page of the NM is not to be subsequently requested by the requesting unit. The MLMC starts a writeback operation of a memory sector including the memory page and one or more additional memory pages. The writeback operation is to transfer the data contained in the memory page from the NM to the FM when the writeback bit is set and the writeback operation does is not to transfer the data contained in the memory page from NM to the FM when the writeback bit is cleared.

    Abstract translation: 描述了多层内存架构技术。 一个处理器包括请求单元，耦合到远存储器（FM）的第一存储器接口，耦合到接近存储器（NM）的第二存储器接口和耦合到请求单元的多级存储器控制器（MLMC） 第一个存储器接口和第二个存储器接口。 MLMC将响应于请求单元从FM获取存储器页面的请求将数据写入NM的存储器页面。 MLMC从请求单元接收提示，并清除提示中指示的内存页的回写位。 提示表明，NM的存储器页面中所包含的数据不会随后由请求单元请求。 MLMC启动包括存储器页面和一个或多个附加存储器页面的存储器扇区的回写操作。 回读操作是当写回位被设置时将存储器页面中包含的从NM的数据传送到FM，并且当回写位被写回时，回写操作确实不会将包含在存储器页面中的数据从NM传送到FM 被清除

    FREQUENCY SELECTION GRANULARITY FOR INTEGRATED CIRCUITS
    26.
    发明申请
    FREQUENCY SELECTION GRANULARITY FOR INTEGRATED CIRCUITS 有权
    用于集成电路的频率选择格局

    公开(公告)号：US20140071784A1

    公开(公告)日：2014-03-13

    申请号：US13730607

    申请日：2012-12-28

    Applicant: HARIKRISHNA B. BALIGA ,  PETER J. SMITH ,  JOYDEEP RAY

    Inventor： HARIKRISHNA B. BALIGA ,  PETER J. SMITH ,  JOYDEEP RAY

    IPC: G11C8/18 ,  H03L7/18

    CPC classification number: G11C8/18 ,  H03L7/07 ,  H03L7/18

    Abstract: Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.

    Abstract translation: 时钟信号发生电路。 耦合倍频器以接收时钟信号并产生倍频时钟信号。 开关电路被耦合以接收至少两个参考时钟信号。 开关电路响应于参考选择信号提供参考时钟信号之一。 耦合锁相环（PLL）以接收倍频时钟信号和所选择的参考时钟信号。 PLL产生输出时钟信号。

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