公开(公告)号：US20180285106A1

公开(公告)日：2018-10-04

申请号：US15477033

申请日：2017-04-01

申请人： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

发明人： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC分类号： G06F9/30 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/46 ,  G09G5/36

摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180285158A1

公开(公告)日：2018-10-04

申请号：US15477026

申请日：2017-04-01

申请人： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

发明人： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC分类号： G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F1/32

摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300238A1

公开(公告)日：2018-10-18

申请号：US15488637

申请日：2017-04-17

申请人： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

发明人： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC分类号： G06F12/06

摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

公开(公告)号：US20180308200A1

公开(公告)日：2018-10-25

申请号：US15494886

申请日：2017-04-24

申请人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06F17/16 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F2009/45583 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type

公开(公告)号：US20180308206A1

公开(公告)日：2018-10-25

申请号：US15698217

申请日：2017-09-07

申请人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08

CPC分类号： G06T1/20 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/1438 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2352/00 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/123 ,  G09G2370/08

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US10649956B2

公开(公告)日：2020-05-12

申请号：US15477027

申请日：2017-04-01

申请人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

发明人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC分类号： G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/0831

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180285374A1

公开(公告)日：2018-10-04

申请号：US15477027

申请日：2017-04-01

申请人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

发明人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC分类号： G06F17/30 ,  G06F9/38 ,  G06F9/30

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180285191A1

公开(公告)日：2018-10-04

申请号：US15477050

申请日：2017-04-01

申请人： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

发明人： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

IPC分类号： G06F11/07

摘要： Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180095785A1

公开(公告)日：2018-04-05

申请号：US15281260

申请日：2016-09-30

申请人： Altug Koker ,  Prassonkumar Surti ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Balaji Vembu

发明人： Altug Koker ,  Prassonkumar Surti ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Balaji Vembu

IPC分类号： G06F9/48

CPC分类号： G06F9/4831 ,  G06F9/4881

摘要： A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a thread dispatcher to assign a priority class to each of a plurality of processing threads prior to dispatching the one or more processing threads, a plurality of execution units to process the threads, a shared resource coupled to each of the plurality of execution units and an arbitration unit to grant access to the shared resource to a first of the plurality of execution units based on the priority class of a thread being executed at the first execution unit.

公开(公告)号：US20190244418A1

公开(公告)日：2019-08-08

申请号：US16269270

申请日：2019-02-06

申请人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC分类号： G06T15/80 ,  G06F9/50 ,  G06T1/20 ,  G06T5/20

CPC分类号： G06T15/80 ,  G06F9/50 ,  G06F9/5011 ,  G06T1/20 ,  G06T5/20

摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.