公开(公告)号：US20090196089A1

公开(公告)日：2009-08-06

申请号：US12232661

申请日：2008-09-22

Applicant: Youn-seon Kang ,  Ki-joon Kim ,  Cheol-kyu Kim ,  Tae-yon Lee

Inventor： Youn-seon Kang ,  Ki-joon Kim ,  Cheol-kyu Kim ,  Tae-yon Lee

IPC: G11C11/00 ,  C01B33/113 ,  C01B21/068 ,  H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1625

Abstract: Disclosed may be a phase change material alloy, a phase change memory device including the same, and methods of manufacturing and operating the phase change memory device. The phase change material alloy may include Si and Sb. The alloy may be a Si—O—Sb alloy further including O. The Si—O—Sb alloy may be SixOySbz, wherein, when x/(x+z) may be x1, 0.05≦x1≦0.30, 0.00≦y≦0.50, and x+y+z may be 1. The Si—O—Sb alloy may further comprise an element other than Si, O, and Sb.

Abstract translation: 公开了相变材料合金，包括该相变材料合金的相变存储器，以及制造和操作相变存储器件的方法。 相变材料合金可以包括Si和Sb。 该合金可以是还包含O的Si-O-Sb合金.Si-O-Sb合金可以是SixOySbz，其中当x /（x + z）可以是x1时，0.05 <= x1 <= 0.30,0.00 < = y <= 0.50，x + y + z可以为1.Si-O-Sb合金还可以包含除Si，O和Sb以外的元素。

公开(公告)号：US20090179185A1

公开(公告)日：2009-07-16

申请号：US12285449

申请日：2008-10-06

Applicant: Youn-seon Kang ,  Daniel Wamwangi ,  Matthias Wuttig ,  Ki-joon Kim ,  Yoon-ho Khang ,  Cheol-kyu Kim ,  Dong-seok Suh ,  Tae-yon Lee

Inventor： Youn-seon Kang ,  Daniel Wamwangi ,  Matthias Wuttig ,  Ki-joon Kim ,  Yoon-ho Khang ,  Cheol-kyu Kim ,  Dong-seok Suh ,  Tae-yon Lee

IPC: H01L47/00 ,  C09K5/00

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1625

Abstract: A phase change material layer includes antimony (Sb) and at least one of indium (In) and gallium (Ga). A phase change memory device includes a storage node including a phase change material layer and a switching device connected to the storage node. The phase change material layer includes Sb and at least one of In and Ga.

Abstract translation: 相变材料层包括锑（Sb）和铟（In）和镓（Ga）中的至少一种。 相变存储器件包括：存储节点，包括相变材料层和连接到存储节点的开关器件。 相变材料层包括Sb和In和Ga中的至少一种。

公开(公告)号：US20080093591A1

公开(公告)日：2008-04-24

申请号：US11907844

申请日：2007-10-18

Applicant: Yoon-ho Khang ,  Ki-Joon Kim ,  Dong-seok Suh

Inventor： Yoon-ho Khang ,  Ki-Joon Kim ,  Dong-seok Suh

IPC: H01L47/00 ,  H01L21/06

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may include a switching device and the storage node. The switching device may be connected to the bottom electrode contact layer. A method of manufacturing the storage node may include forming a via hole in an insulating interlayer, at least partially filling the via hole to form a bottom electrode contact layer, protruding the bottom electrode contact layer from the via hole, and forming a phase change layer that covers the bottom electrode contact layer. A method of manufacturing a phase change memory device may include forming the switching device on a substrate and manufacturing the storage node.

Abstract translation: 存储节点可以包括底部电极接触层，连接到底部电极接触层的相变层和连接到相变层的顶部电极层。 底部电极接触层可以向相变层突出。 相变存储器件可以包括切换装置和存储节点。 开关器件可以连接到底部电极接触层。 制造存储节点的方法可以包括在绝缘中间层中形成通孔，至少部分地填充通孔以形成底电极接触层，从底孔电极接触层从通孔突出，并形成相变层 覆盖底部电极接触层。 相变存储器件的制造方法可以包括在基板上形成开关器件并制造存储节点。

公开(公告)号：US20070184613A1

公开(公告)日：2007-08-09

申请号：US11703126

申请日：2007-02-07

Applicant: Ki-Joon Kim ,  Yoon-Ho Khang ,  Jin-Seo Noh

Inventor： Ki-Joon Kim ,  Yoon-Ho Khang ,  Jin-Seo Noh

IPC: H01L21/336

CPC classification number: H01L29/8615 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/73 ,  H01L29/24 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A phase change RAM (PRAM) including a resistance element having a diode function, and methods of fabricating and operating the same are provided. The PRAM may include a substrate, a phase change diode layer formed on the substrate and an upper electrode formed on the phase change diode layer. The phase change diode layer may include a material layer doped with first impurities, and a phase change layer which is stacked on the doped layer. The phase change layer may show characteristics of a semiconductor material doped with impurities having an opposite conductive type to that of the first impurities.

Abstract translation: 提供了包括具有二极管功能的电阻元件的相变RAM（PRAM）及其制造和操作方法。 PRAM可以包括衬底，形成在衬底上的相变二极管层和形成在相变二极管层上的上电极。 相变二极管层可以包括掺杂有第一杂质的材料层和层叠在掺杂层上的相变层。 相变层可以显示掺杂有与第一杂质导电类型相反的导电类型的杂质的半导体材料的特性。

公开(公告)号：US20060071898A1

公开(公告)日：2006-04-06

申请号：US11245279

申请日：2005-10-06

Applicant: Ki-joon Kim

Inventor： Ki-joon Kim

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0248 ,  G09G2330/023

Abstract: A source driver output circuit of a thin film transistor (TFT) liquid crystal display (LCD) includes first through n-th voltage generators, first through n-th switching portions, first through n-th sub switching portions, and a switching circuit. The voltage generators receive first through n-th corresponding input voltages and generate first through n-th sub input voltages. The switching portions generate the sub input voltages as first through n-th corresponding output voltages when activated, or cut off the sub input voltages when deactivated. The sub switching portions connect predetermined share lines to the output voltages when activated, or cut off the predetermined share lines when deactivated. The switching circuit maintains each of the share line voltages equally at an intermediate voltage level that is between the share line voltages. Therefore, the slew rate of a signal input to the panel from the source driver can be improved, and current consumption in the source driver can be reduced.

Abstract translation: 薄膜晶体管（TFT）液晶显示器（LCD）的源极驱动器输出电路包括第一至第n电压发生器，第一至第n开关部分，第一至第N子切换部分和开关电路。 电压发生器接收第一至第n对应的输入电压，并产生第一至第n子输入电压。 开关部分在激活时产生作为第一至第n对应的输出电压的子输入电压，或者在去激活时切断子输入电压。 子开关部分在激活时将预定的共享线路连接到输出电压，或者在停用时切断预定共享线路。 开关电路将共享线路电压中的每一个均等于在共享线路电压之间的中间电压电平。 因此，可以提高从源极驱动器输入到面板的信号的转换速率，并且可以减少源极驱动器中的电流消耗。

公开(公告)号：US06954192B2

公开(公告)日：2005-10-11

申请号：US10283974

申请日：2002-10-30

Applicant: Ki-joon Kim

Inventor： Ki-joon Kim

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0248 ,  G09G2330/023

Abstract: A source driver output circuit of a thin film transistor (TFT) liquid crystal display (LCD) includes first through n-th voltage generators, first through n-th switching portions, first through n-th sub switching portions, and a voltage-generating portion. The voltage generators receive first through n-th corresponding input voltages and generate first through n-th sub input voltages. The switching portions generate the sub input voltages as first through n-th corresponding output voltages when activated, or cut off the sub input voltages when deactivated. The sub switching portions connect predetermined share lines to the output voltages when activated, or cut off the predetermined share lines when deactivated. The voltage-generating portion receives predetermined first and second voltages and applies predetermined precharge voltages to the share lines. Therefore, the slew rate of a signal input to the panel from the source driver can be improved, and current consumption in the source driver can be reduced.

Abstract translation: 薄膜晶体管（TFT）液晶显示器（LCD）的源极驱动器输出电路包括第一至第n电压发生器，第一至第n开关部分，第一至第N子切换部分和产生电压 一部分。 电压发生器接收第一至第n对应的输入电压，并产生第一至第n子输入电压。 开关部分在激活时产生作为第一至第n对应的输出电压的子输入电压，或者在去激活时切断子输入电压。 子开关部分在激活时将预定的共享线路连接到输出电压，或者在停用时切断预定共享线路。 电压产生部分接收预定的第一和第二电压并且向共享线路施加预定的预充电电压。 因此，可以提高从源极驱动器输入到面板的信号的转换速率，并且可以减少源极驱动器中的电流消耗。

公开(公告)号：US6147385A

公开(公告)日：2000-11-14

申请号：US218819

申请日：1998-12-22

Applicant: Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

Inventor： Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

IPC: H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L27/11 ,  H01L27/1104 ,  Y10S257/903

Abstract: A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions. The drain region of the second load transistor is disposed between the drain region of the first load transistor and the second common region. First and second gate electrode layers are disposed generally parallel to each other, and respectively serving as the gates of the first driving transistor and the first load transistor and as the gates of the second driving transistor and the second load transistor, wherein each of the first and second gate electrode layers is made of a conductive material of a first level. First and second interconnecting layers are each made of a conductive material of a second level different from the first level, the first interconnecting layer connecting the first common region to the drain region of the first load transistor and the second gate electrode layer, the second interconnecting layer connecting the second common region to the drain region of the second load transistor and the first gate electrode layer.

Abstract translation: 描述具有减小的纵横比的能力的完整CMOS SRAM单元。 SRAM单元包括n沟道类型的第一和第二传输晶体管，n沟道类型的第一和第二驱动晶体管以及p沟道类型的第一和第二负载晶体管。 每个晶体管在形成在半导体衬底中的沟道区的相对侧上具有源极和漏极区域，并且在沟道区域上具有栅极。 单元包括由第一传输晶体管的漏极区域和串联连接的第一驱动晶体管限定的第一公共区域。 第二公共区域由第二传输晶体管和串联连接的第二驱动晶体管的漏极区限定。 第一负载晶体管的漏极区域设置成与第一和第二公共区域之间的第一公共区域相邻。 第二负载晶体管的漏极区域设置在第一负载晶体管的漏极区域和第二公共区域之间。 第一和第二栅极电极层大体上彼此平行地设置，并且分别用作第一驱动晶体管和第一负载晶体管的栅极，以及作为第二驱动晶体管和第二负载晶体管的栅极，其中第一 并且第二栅电极层由第一级的导电材料制成。 第一和第二互连层各自由不同于第一电平的第二电平的导电材料制成，第一互连层将第一公共区域连接到第一负载晶体管的漏极区域和第二栅极电极层，第二互连 将第二公共区域连接到第二负载晶体管的漏极区域和第一栅极电极层的层。

公开(公告)号：US09379003B2

公开(公告)日：2016-06-28

申请号：US14053932

申请日：2013-10-15

Applicant: Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

Inventor： Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/7681 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

Abstract translation: 公开了一种半导体器件和形成半导体器件的方法。 在该方法中，在衬底上形成诸如绝缘中间层的层。 在该层中形成第一沟槽，并且在第一沟槽中形成掩模层。 掩模层具有从第一沟槽的底表面到掩模层的顶部的第一厚度。 图案化掩模层以形成至少部分地暴露第一沟槽的侧壁的掩模。 与第一沟槽的暴露的侧壁相邻的掩模的一部分具有小于第一厚度的第二厚度。 使用掩模作为蚀刻掩模蚀刻该层以形成第二沟槽。 第二沟槽与第一沟槽流体连通。 在第一沟槽和第二沟槽中形成导电图案。

公开(公告)号：US08823119B2

公开(公告)日：2014-09-02

申请号：US13682737

申请日：2012-11-21

Applicant: Ki-joon Kim ,  Hyung-joon Kwon

Inventor： Ki-joon Kim ,  Hyung-joon Kwon

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L29/82 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

Abstract translation: 一种磁体结构，包括：磁性层图案; 以及包括金属玻璃合金并覆盖至少一部分磁体结构的导电图案。

公开(公告)号：US20110233698A1

公开(公告)日：2011-09-29

申请号：US13070890

申请日：2011-03-24

Applicant: Ki Joon KIM

Inventor： Ki Joon KIM

IPC: H01L29/82

CPC classification number: H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3263 ,  H01F41/307 ,  H01L43/10

Abstract: Provided is a magnetic memory device and a method of forming the same. A first magnetic conductive layer is disposed on a substrate. A first tunnel barrier layer including a first metallic element and a first non-metallic element is disposed on the first magnetic conductive layer. A second magnetic conductive layer is disposed on the first tunnel barrier layer. A content of an isotope of the first metallic element having a non-zero nuclear spin quantum number is lower than a natural state.

Abstract translation: 提供一种磁存储器件及其形成方法。 第一导电层设置在基板上。 包括第一金属元件和第一非金属元件的第一隧道势垒层设置在第一导电层上。 第二导电层设置在第一隧道势垒层上。 具有非零核自旋量子数的第一金属元素的同位素含量低于自然状态。