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    Schottky-barrier tunneling transistor
    23.
    发明授权
    Schottky-barrier tunneling transistor 失效
    肖特基势垒隧道晶体管

    公开(公告)号：US06744111B1

    公开(公告)日：2004-06-01

    申请号：US10438674

    申请日：2003-05-15

    Applicant: Koucheng Wu

    Inventor： Koucheng Wu

    IPC: H01L27095

    CPC classification number: H01L27/1203 ,  H01L21/84

    Abstract: A three-terminal semiconductor transistor device comprises a semiconductor base region in contact with a first electric terminal, a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region. The conductive emitter region is in contact with a second electric terminal. The three-terminal semiconductor transistor device further includes a conductive collector region in contact with the semiconductor base region, forming a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region. The conductive collector region is in contact with a third electric terminal. The tunneling currents through the first and the second Schottky barrier junctions are substantially controlled by the voltage of the semiconductor base region.

    Abstract translation: 三端子半导体晶体管器件包括与第一电端子接触的半导体基极区域，与半导体基极区域接触的导电发射极区域，在导电发射极区域和半导体基底的界面处形成第一肖特基势垒结 地区。 导电发射极区域与第二电端子接触。 三端子半导体晶体管器件还包括与半导体基极区域接触的导电集电极区域，在导电集电极区域和半导体基极区域的界面处形成第二肖特基势垒结。 导电集电极区域与第三电端子接触。 通过第一和第二肖特基势垒结的隧道电流基本上由半导体基极区域的电压控制。

    Device and method for work function reduction and thermionic energy conversion
    25.
    发明授权
    Device and method for work function reduction and thermionic energy conversion 有权

    公开(公告)号：US11496072B2

    公开(公告)日：2022-11-08

    申请号：US16867743

    申请日：2020-05-06

    Applicant: Koucheng Wu

    Inventor： Koucheng Wu

    IPC: H02N3/00 ,  H01L29/12 ,  H01L31/0352 ,  H01L29/66

    Abstract: A quantum wire device includes a barrier formed by an insulator or a wide bandgap semiconductor, and metal quantum wires comprising a metal material and embedded in the barrier. Potential wells are formed for electrons in the metal quantum wires by the insulator or the wide bandgap semiconductor. The work function of the metal quantum wires is reduced by quantum confinement compared to a bulk form of the metal material. The metal quantum wires are electrically connected. The metal quantum wires include an exposed active area for electron emission or electron collection.

    Quantum Wire Resonant Tunneling Transistor
    26.
    发明申请
    Quantum Wire Resonant Tunneling Transistor 有权

    公开(公告)号：US20210328015A1

    公开(公告)日：2021-10-21

    申请号：US16852493

    申请日：2020-04-19

    Applicant: Koucheng Wu

    Inventor： Koucheng Wu

    IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/73 ,  H01L29/66 ,  H01L29/04 ,  H01L29/16

    Abstract: A semiconductor transistor device includes an emitter region that includes a plurality of metal quantum wires and is connected to an emitter terminal, a base region that includes a plurality of metal quantum wires and is connected to a base terminal, a collector region comprising a plurality of metal quantum wires and is connected to a collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region.

    Device and Method for Work Function Reduction and Thermionic Energy Conversion
    27.
    发明申请
    Device and Method for Work Function Reduction and Thermionic Energy Conversion 审中-公开

    公开(公告)号：US20200266040A1

    公开(公告)日：2020-08-20

    申请号：US16867743

    申请日：2020-05-06

    Applicant: Koucheng Wu

    Inventor： Koucheng Wu

    IPC: H01J45/00

    Abstract: A quantum wire device includes a barrier formed by an insulator or a wide bandgap semiconductor, and metal quantum wires comprising a metal material and embedded in the barrier. Potential wells are formed for electrons in the metal quantum wires by the insulator or the wide bandgap semiconductor. The work function of the metal quantum wires is reduced by quantum confinement compared to a bulk form of the metal material. The metal quantum wires are electrically connected. The metal quantum wires include an exposed active area for electron emission or electron collection.

    Schottky barrier quantum well resonant tunneling transistor
    28.
    发明授权
    Schottky barrier quantum well resonant tunneling transistor 有权
    肖特基势垒量子阱谐振隧穿晶体管

    公开(公告)号：US07936040B2

    公开(公告)日：2011-05-03

    申请号：US12258425

    申请日：2008-10-26

    Applicant: Koucheng Wu

    Inventor： Koucheng Wu

    IPC: H01L29/47

    CPC classification number: H01L29/7322 ,  H01L27/0605 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0821 ,  H01L29/152 ,  H01L29/20 ,  H01L29/73 ,  H01L29/7308

    Abstract: A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 Å. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.

    Abstract translation: 半导体晶体管器件包括一个或多个导电基极区域，第一半导体势垒区域，第二半导体势垒区域，导电发射极区域和导电收集区域。 第一半导体势垒区域或第二半导体势垒区域的尺寸小于100埃。 在第一半导体势垒区域和一个或多个导电基极区域的界面处形成第一肖特基势垒结。 在第二半导体阻挡区域和一个或多个导电基极区域的界面处形成第二肖特基势垒结。 在导电发射极区域和第一半导体势垒区域的界面处形成第三肖特基势垒结。 第四肖特基势垒结形成在导电集电区和第二半导体势垒区的界面处。

    Nonvolatile memory with a unified cell structure
    29.
    发明授权
    Nonvolatile memory with a unified cell structure 有权
    具有统一单元结构的非易失性存储器

    公开(公告)号：US07636252B2

    公开(公告)日：2009-12-22

    申请号：US11483241

    申请日：2006-07-07

    Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

    Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

    IPC: G11C16/04

    CPC classification number: H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

    Abstract translation: 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

    NOR-type channel-program channel-erase contactless flash memory on SOI
    30.
    发明申请
    NOR-type channel-program channel-erase contactless flash memory on SOI 审中-公开
    SOI上的NOR型通道编程通道擦除非接触式闪存

    公开(公告)号：US20090029511A1

    公开(公告)日：2009-01-29

    申请号：US11193652

    申请日：2005-08-01

    Applicant: Koucheng Wu

    Inventor： Koucheng Wu

    IPC: H01L21/336

    CPC classification number: G11C16/3404 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/0491 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7881

    Abstract: A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

    Abstract translation: 具有电可擦除可编程只读存储器（EEPROM）的半导体器件包括以行和列布置并构造在绝缘体上硅晶片上的EEPROM存储器单元的非接触阵列。 每个EEPROM存储单元包括漏极区域，源极区域，栅极区域和体区域。 半导体器件还包括多条栅极线，每条栅极线连接一行EEPROM存储器单元的栅极区域，多个体线，每条主体线连接EEPROM存储单元列的主体区域;多个源极线，每条源极线连接源极 一列EEPROM存储单元的区域，以及各自连接EEPROM存储单元列的漏区的多条漏极线。 源极线和漏极线为掩埋线，并且EEPROM存储单元的列的源极区域和漏极区域与EEPROM存储器单元的相邻列的源极区域和漏极区域绝缘。

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