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    NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY
    21.
    发明申请
    NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY 审中-公开
    基于非均匀开关的非易失性磁性存储器

    公开(公告)号：US20120069643A1

    公开(公告)日：2012-03-22

    申请号：US13305677

    申请日：2011-11-28

    Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: G11C11/00

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

    Abstract translation: 非均匀开关型非易失性磁存储元件包括固定层，形成在固定层顶部上的阻挡层，形成在阻挡层顶部上的第一自由层，形成非均匀开关层（NSL） 在第一自由层的顶部和形成在不均匀开关层的顶部上的第二自由层。 在基本上垂直于固定层，阻挡层，第一自由层，不均匀的开关层和第二自由层的方向上施加开关电流，导致第一自由层，第二自由层和非自由层的状态之间的切换， 均匀的开关层，开关电流大大降低。

    Non-uniform switching based non-volatile magnetic based memory
    23.
    发明授权
    Non-uniform switching based non-volatile magnetic based memory 有权
    基于非均匀开关的非易失性磁性存储器

    公开(公告)号：US08084835B2

    公开(公告)日：2011-12-27

    申请号：US11674124

    申请日：2007-02-12

    Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: H01L29/82 ,  G11C11/00

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

    Abstract translation: 非均匀开关型非易失性磁存储元件包括固定层，形成在固定层顶部上的阻挡层，形成在阻挡层顶部上的第一自由层，形成非均匀开关层（NSL） 在第一自由层的顶部和形成在不均匀开关层的顶部上的第二自由层。 在基本上垂直于固定层，阻挡层，第一自由层，不均匀的开关层和第二自由层的方向上施加开关电流，导致第一自由层，第二自由层和非自由层的状态之间的切换， 均匀的开关层，开关电流大大降低。

    Direct logical block addressing flash memory mass storage architecture
    24.
    发明授权
    Direct logical block addressing flash memory mass storage architecture 有权
    直接逻辑块寻址闪存大容量存储架构

    公开(公告)号：US08032694B2

    公开(公告)日：2011-10-04

    申请号：US12844354

    申请日：2010-07-27

    Applicant: Petro Estakhri ,  Mahmud Assar

    Inventor： Petro Estakhri ,  Mahmud Assar

    IPC: G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

    CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

    Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

    Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

    Flash memory card with enhanced operating mode detection and user-friendly interfacing system
    25.
    发明授权
    Flash memory card with enhanced operating mode detection and user-friendly interfacing system 有权

    公开(公告)号：US07111085B2

    公开(公告)日：2006-09-19

    申请号：US10647084

    申请日：2003-08-21

    Applicant: Petro Estakhri ,  Mahmud Assar

    Inventor： Petro Estakhri ,  Mahmud Assar

    IPC: G06F3/00

    CPC classification number: G11C7/20 ,  G06F13/387 ,  G06F13/4081 ,  G06F2213/0042 ,  G11C7/1045

    Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols.

    Precision clock synthesizer using RC oscillator and calibration circuit
    26.
    发明授权
    Precision clock synthesizer using RC oscillator and calibration circuit 有权
    精密时钟合成器采用RC振荡器和校准电路

    公开(公告)号：US06404246B1

    公开(公告)日：2002-06-11

    申请号：US09741971

    申请日：2000-12-20

    Applicant: Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    Inventor： Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

    IPC: H03L706

    CPC classification number: H03L7/18 ,  H03K3/0231 ,  H03L7/087

    Abstract: A system and method of generating an output signal of very precise frequency without the use of a crystal oscillator. An input signal is generated using any convenient such as an RC oscillator. A circuit for producing a frequency-controlled output signal comprises a phase lock loop having a VCO and a down counter. The down counter reduces the frequency of a VCO clock signal in accordance with a down count value. The down count value is loaded in a register and stored in non-volatile memory. The down count value is set during a calibration operation using a precision external clock signal. In this way, a clock signal with a highly precise frequency is generated without using a crystal oscillator.

    Abstract translation: 一种在不使用晶体振荡器的情况下产生非常精确频率的输出信号的系统和方法。 使用任何方便的RC振荡器产生输入信号。 用于产生频率控制的输出信号的电路包括具有VCO和向下计数器的锁相环。 下降计数器根据递减计数值降低VCO时钟信号的频率。 递减计数值加载到寄存器中并存储在非易失性存储器中。 在使用精密外部时钟信号的校准操作期间设置递减计数值。 以这种方式，在不使用晶体振荡器的情况下产生具有高精度频率的时钟信号。

    System for configuring a flash memory card with enhanced operating mode detection and user-friendly interfacing system
    27.
    发明授权
    System for configuring a flash memory card with enhanced operating mode detection and user-friendly interfacing system 有权
    用于通过监视来自主机的未编码信号和卡中的编码信号来将闪存卡配置到所选操作模式的系统

    公开(公告)号：US06385667B1

    公开(公告)日：2002-05-07

    申请号：US09234430

    申请日：1999-01-20

    Applicant: Petro Estakhri ,  Mahmud Assar

    Inventor： Petro Estakhri ,  Mahmud Assar

    IPC: G06F1314

    CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

    Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with the interface device, the flash memory card automatically detects the selected operating mode of the interface device and configures itself to operate with the selected operating mode. The operating mode detection is accomplished by sensing unencoded signals and encoded signals. The encoded signals are encoded with a finite set of predetermined codes. Each predetermined code uniquely identifies a particular operating mode.

    Abstract translation: 一种接口系统，在主计算机系统和闪存卡之间以选定的操作模式促进用户友好的连接。 接口系统包括接口设备和闪存卡。 接口系统具有显着扩展闪存卡内的工作模式检测功能，并显着减少了操作模式的错误检测。 接口设备包括用于耦合到主计算机的第一端和用于耦合到闪存卡的第二端，同时支持主机计算机系统也支持的所选操作模式中的通信。 闪存卡利用五十针连接通过接口设备与主机系统进行接口。 闪存卡的五十针连接可以在各种配置中使用，例如通用串行模式，PCMCIA模式和ATA IDE模式。 这些操作模式中的每一种都需要不同的协议。 在使用接口设备进行初始化时，闪存卡会自动检测接口设备的选定操作模式，并配置自身以所选择的操作模式进行操作。 通过感测未编码的信号和编码信号来实现操作模式检测。 编码信号用有限的一组预定码进行编码。 每个预定代码唯一地标识特定的操作模式。

    Programmable tiles
    28.
    发明授权
    Programmable tiles 失效
    可编程瓷砖

    公开(公告)号：US5157618A

    公开(公告)日：1992-10-20

    申请号：US486337

    申请日：1990-02-28

    Applicant: H. Ravindra ,  Suhas S. Patil ,  Ernest S. Lin ,  Mahmud Assar ,  Dayakar Reddy

    Inventor： H. Ravindra ,  Suhas S. Patil ,  Ernest S. Lin ,  Mahmud Assar ,  Dayakar Reddy

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/1735 ,  H03K19/1736 ,  H03K19/17712

    Abstract: Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approaching those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.

    Abstract translation: 公开了一组由部分子门元件构成的功能部件（瓦片），其通过其设计有助于创建密集的集成电路，而不会通过后期掩模编程技术来丧失修改各个瓦片的功能的能力。 通过手工制作的定制设计获得的总体密度可以部分地被获得，这是因为这样的部件设计成在整个存储逻辑阵列中被平铺，允许创建正交逻辑门以及单独的门（和更复杂的功能） 其功能水平，垂直分布，甚至以锯齿形的方式分布。 此外，由于易于修复和增强复杂功能，从原型到大批量制造的转换时间显着减少。

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