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公开(公告)号：US6125056A
公开(公告)日：2000-09-26
申请号：US291865
申请日：1999-04-14
Applicant: Johnny Chen , Tiao-Hua Kuo , Nancy Leong
Inventor： Johnny Chen , Tiao-Hua Kuo , Nancy Leong
CPC classification number: G11C16/10
Abstract: A method for fast programming of non-volatile memory cells in a non-volatile memory array comprises the steps of providing an acceleration voltage greater than the internal pump voltage supplied by a conventional internal drain pump, providing a program write command, and coupling the acceleration voltage to provide a programming current to all of the bit lines selected to be programmed at a time. In an embodiment, the acceleration voltage is reduced to a drain voltage before it is applied to the drains of the memory cells. In an embodiment in which the flash memory cells comprise typical dual-gate NOR devices, the acceleration voltage is in the range of about 7 V to about 10 V, and the drain voltage is on the order of about 5 V. The sources of the memory cells are grounded during the fast programming operation. In a further embodiment, the method further comprises the steps of detecting the acceleration voltage, generating an acceleration voltage indicator signal in response to the presence of the acceleration voltage, and generating a fast program write command in response to the acceleration voltage indicator signal and the program write command to set the flash memory cells in a fast program mode.
Abstract translation: 用于在非易失性存储器阵列中快速编程非易失性存储器单元的方法包括以下步骤：提供大于由常规内部排水泵提供的内部泵浦电压的加速电压，提供程序写入命令，以及耦合加速度 电压以将编程电流提供给所选择的一次编程的位线。 在一个实施例中，加速电压在被施加到存储器单元的漏极之前被减小到漏极电压。 在闪存单元包括典型的双栅极NOR器件的实施例中，加速电压在约7V至约10V的范围内，漏极电压约为5V左右。源 存储单元在快速编程操作期间接地。 在另一实施例中，该方法还包括以下步骤：检测加速电压，响应加速电压的存在产生加速电压指示信号，并响应加速电压指示信号产生快速程序写命令 程序写入命令以快速程序模式设置闪存单元。
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公开(公告)号：US08264898B2
公开(公告)日：2012-09-11
申请号：US13156763
申请日：2011-06-09
Applicant: Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
Inventor： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC: G11C7/00
CPC classification number: G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。
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公开(公告)号：US20110235412A1
公开(公告)日：2011-09-29
申请号：US13156763
申请日：2011-06-09
Applicant: Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
Inventor： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC: G11C16/04
CPC classification number: G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。
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公开(公告)号：US20100103732A1
公开(公告)日：2010-04-29
申请号：US12650118
申请日：2009-12-30
Applicant: Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
Inventor： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
CPC classification number: G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。
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Patent Agency Ranking
公开(公告)号：US07307878B1
公开(公告)日：2007-12-11
申请号：US11212850
申请日：2005-08-29
Applicant: Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
Inventor： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
CPC classification number: G11C16/0475 , G11C16/3454 , G11C16/3459
Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.
Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。
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公开(公告)号：US20070165458A1
公开(公告)日：2007-07-19
申请号：US11332241
申请日：2006-01-17
Applicant: Nancy Leong , Sachit Chandra , Hounien Chen
Inventor： Nancy Leong , Sachit Chandra , Hounien Chen
IPC: G11C16/04
CPC classification number: G11C16/26 , G06F12/0893 , G06F2212/2022 , G11C7/1039
Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.
Abstract translation: 诸如闪存的非易失性存储器被配置为执行随机的多页读取操作。 存储器可以包括非易失性存储器单元的核心阵列和用于接收随机多页读取操作的指示的输入线。 此外，存储器可以包括耦合到核心阵列的多级易失性存储器，其被配置为以流水线方式从核心阵列同时处理多个数据页面。 输出线耦合到多级易失性存储器并从存储器件输出数据页面。
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27.发明授权Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture 有权制造灵活划分的金属线段的方法，用于具有灵活的银行分区架构的同时操作的闪存设备
公开(公告)号：US6033955A
公开(公告)日：2000-03-07
申请号：US159023
申请日：1998-09-23
Applicant: Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
Inventor： Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
IPC: G11C16/04 , G11C5/00 , G11C8/10 , G11C8/12 , G11C16/08 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
Abstract: A method of forming flexibly partitioned metal line segments 10 and 12 for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer 2 comprising a plurality of basic metal layer segments 2a, 2b, 2c, . . . 2j separated by a plurality of gaps 6a, 6b, 6c, . . . 6i, each of the gaps having a predefined gap interval length, and providing a metal option layer 8 comprising a plurality of metal option layer segments on the basic metal layer 2, the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.
Abstract translation: 在具有柔性库分隔结构的同时操作的闪速存储器件中形成用于单独存储体的柔性分隔的金属线段10和12的方法包括以下步骤：提供包括多个基本金属层段2a，2b的基本金属层2 ，2c，。 。 。 2j由多个间隙6a，6b，6c，...分开。 。 。 如图6i所示，每个间隙具有预定的间隙间隔长度，并且提供包括在基本金属层2上的多个金属可选层段的金属选择层8，金属选择层段与基本金属层段之间的间隙重叠，但是 留下一个间隙打开，以形成用于单独存储体的金属线段。
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28.发明授权Memory address decoding circuit for a simultaneous operation flash memory device with a flexible bank partition architecture 有权存储器地址解码电路，用于同时运行闪存器件，具有灵活的存储体分区结构
公开(公告)号：US06005803A
公开(公告)日：1999-12-21
申请号：US159342
申请日：1998-09-23
Applicant: Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
Inventor： Tiao-Hua Kuo , Yasushi Kasa , Nancy Leong , Johnny Chen , Michael Van Buskirk
Abstract: A decoding circuit 54 for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder 44, a lower bank decoder 58, an upper bank decoder 56, and a plurality of flexibly partitioned conductive lines coupled between the upper and lower bank decoders 56 and 58. The flexibly partitioned conductive lines 60, 62, 64, . . . 74 provide a plurality of bank address pre-decoding bits for the X-decoder 44 to row decode the memory cells along the respective word lines in the memory array 20. The memory array 20 includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are coupled to two Y-decoders 32 and 34 which provide column decoding for the memory cells in the upper and lower memory banks.
Abstract translation: 用于具有灵活存储体分区体系结构的同时操作的非易失性存储器件的解码电路54包括X解码器44，下部存储体解码器58，上部存储体解码器56和多个柔性分隔的导线， 和下部分组解码器56和58.柔性分隔的导线60,62,64。 。 。 74提供多个用于X解码器44的存储体地址预解码位，以沿着存储器阵列20中的相应字线对存储器单元进行解码。存储器阵列20包括多个灵活分割的位线，包括第一和第二 位线段将存储器阵列分隔成上部和下部存储体。 上存储体和下存储体中的位线段耦合到两个Y解码器32和34，它们为上和下存储体中的存储单元提供列解码。
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29.发明授权Overerase correction for flash memory which limits overerase and prevents erase verify errors 失效对闪存进行过度修正，限制过高，并防止擦除验证错误
公开(公告)号：US5642311A
公开(公告)日：1997-06-24
申请号：US547494
申请日：1995-10-24
Applicant: Lee Cleveland , Chung Chang , Yuan Tang , Nancy Leong , Michael Fliesler , Tiao-Hua Kuo
Inventor： Lee Cleveland , Chung Chang , Yuan Tang , Nancy Leong , Michael Fliesler , Tiao-Hua Kuo
CPC classification number: G11C16/3409 , G11C16/3404 , G11C16/3445
Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.
Abstract translation: 一种包括闪存EEPROM存储单元阵列的集成电路，其中在施加每个擦除脉冲之后提供过电压校正。
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