公开(公告)号：US20120238050A1

公开(公告)日：2012-09-20

申请号：US13460333

申请日：2012-04-30

Applicant: Zhi-Wen Sun ,  Nitin Kumar ,  Guizhen Zhang ,  Nikhil Kalyankar ,  Minh Anh Nguyen

Inventor： Zhi-Wen Sun ,  Nitin Kumar ,  Guizhen Zhang ,  Nikhil Kalyankar ,  Minh Anh Nguyen

IPC: H01L31/18

CPC classification number: B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00536 ,  B01J2219/00596 ,  B01J2219/00702 ,  B01J2219/00754 ,  B01J2219/00756 ,  C40B40/18 ,  C40B60/14 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/1884 ,  Y02E10/50

Abstract: Embodiments of the current invention include methods of improving a process of forming a textured TCO film by combinatorial methods. The combinatorial method may include depositing a TCO by physical vapor deposition or sputtering, annealing the TCO, and etching the TCO where at least one of the depositing, the annealing, or the etching is performed combinatorially. Embodiments of the current invention also include improved methods of forming the TCO based on the results of combinatorial testing.

Abstract translation: 本发明的实施例包括通过组合方法改进形成纹理TCO膜的工艺的方法。 组合方法可以包括通过物理气相沉积或溅射沉积TCO，退火TCO，以及蚀刻TCO，其中组合进行沉积，退火或蚀刻中的至少一个。 本发明的实施例还包括基于组合测试的结果形成TCO的改进方法。

公开(公告)号：US08077726B1

公开(公告)日：2011-12-13

申请号：US12391859

申请日：2009-02-24

Applicant: Nitin Kumar ,  Alex Baban

Inventor： Nitin Kumar ,  Alex Baban

IPC: H04L12/56

CPC classification number: H04L45/00 ,  H04L41/0893 ,  H04L45/22 ,  H04L45/28 ,  H04L45/50 ,  H04L45/507 ,  H04L45/52 ,  H04W8/18 ,  H04W40/00 ,  H04W88/16

Abstract: Techniques are described for maintaining a forwarding information base (FIB) within a packet-forwarding engine (PFE) of a router, and programming a packet-forwarding integrated circuit (IC) with a hardware version of the FIB. Entries of the hardware version identify primary forwarding next hops and backup forwarding next hops for the LSPs, wherein the packet-forwarding IC includes a control logic module and internal selector block configured to produce a value indicating a state of the first physical link. The selector block outputs one of the primary forwarding next hop and the backup forwarding next hop of the entries for forwarding the MPLS packets based on the value in response to the packet-processing engine addressing one of the entries of the FIB for the LSPs. Packets are forwarded with the PFE to the one of the primary forwarding next hop and the backup forwarding next hop output by the selector block.

Abstract translation: 描述了用于在路由器的分组转发引擎（PFE）内维护转发信息库（FIB）的技术，并且利用FIB的硬件版本来编程分组转发集成电路（IC）。 硬件版本的条目识别LSP的主转发下一跳和后续转发，其中分组转发IC包括控制逻辑模块和内部选择器块，其被配置为产生指示第一物理链路的状态的值。 选择器块输出主要转发下一跳和用于转发MPLS分组的条目的备用转发下一跳，该响应于响应于分组处理引擎寻址用于LSP的FIB的条目中的一个的值。 分组与PFE一起转发到主转发下一跳和选择器块下一跳输出的备份转发。

公开(公告)号：US20110302455A1

公开(公告)日：2011-12-08

申请号：US12794781

申请日：2010-06-07

Applicant: Gavin Shane Thomas ,  Nitin Kumar Goel ,  Mark Wodrich

Inventor： Gavin Shane Thomas ,  Nitin Kumar Goel ,  Mark Wodrich

IPC: G06F11/00 ,  G06N5/02

CPC classification number: G06F11/3636 ,  G06F11/3684 ,  G06F21/577

Abstract: Technologies are described herein for performing targeted, black-box fuzzing of input data for application testing. A dataflow tracing module traces an application while it reads and processes a set of template data to produce operation mapping data that maps data locations in the template data to operations performed by the application in processing the data at the location. The tracing is performed without requiring the application source code, knowledge of the syntactical structure of the input data, or specially instrumented binaries for the application. A fuzzing module is then utilized to target a specific operation or operations in the application by fuzzing data locations within the template data according to the operation mapping data until the desired outcome is achieved.

Abstract translation: 本文描述了技术，用于执行用于应用测试的输入数据的目标黑盒模糊。 数据流跟踪模块在读取和处理一组模板数据时跟踪应用程序，以产生将模板数据中的数据位置映射到应用程序执行的操作的操作映射数据，以处理该位置的数据。 执行跟踪，而不需要应用程序源代码，输入数据的语法结构的知识或应用程序的特殊检测的二进制文件。 然后，利用模糊模块来根据操作映射数据通过模糊数据位置来模拟应用程序中的特定操作或操作，直到达到期望的结果。

公开(公告)号：US07704789B2

公开(公告)日：2010-04-27

申请号：US11702967

申请日：2007-02-05

Applicant: Zhi-wen Sun ,  Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang

Inventor： Zhi-wen Sun ,  Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang

IPC: H01L21/00

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract translation: 提供电阻式开关存储器元件，其可以包含由无电金属形成的化学金属电极和金属氧化物。 电阻式开关存储器元件可以表现出双稳态，并且可以用于高密度多层存储器集成电路中。 诸如镍基材料的无电导电材料可以选择性地沉积在硅晶片或其它合适的衬底上的导体上。 无电导电材料可以被氧化以形成用于电阻式开关存储元件的金属氧化物。 可以沉积多层导电材料，每层具有不同的氧化速率。 可以利用导电层的差异氧化速率来确保在制造期间形成所需厚度的金属氧化物层。

公开(公告)号：US20090200955A1

公开(公告)日：2009-08-13

申请号：US12029811

申请日：2008-02-12

Applicant: Istvan Maros ,  Istvan Peter Bakk ,  Louis R. Nerone ,  Timothy Chen ,  Nitin Kumar

Inventor： Istvan Maros ,  Istvan Peter Bakk ,  Louis R. Nerone ,  Timothy Chen ,  Nitin Kumar

IPC: H05B41/36 ,  H05B41/24

CPC classification number: H05B35/00 ,  H01J61/327 ,  H05B41/2827

Abstract: A circuit or combined ballast for driving a fluorescent lamp and at least one light emitting diode (LED) includes an integrated driver circuit having an alternating current (AC) circuit that includes at least one ballast coil for driving the fluorescent lamp and a direct current circuit for driving the LED having a secondary winding inductively coupled with the fluorescent lamp ballast coil for driving the LED. A method of driving a lamp assembly includes at least one fluorescent lamp and at least one light emitting diode (LED) and a combined driver circuit for supplying both the fluorescent lamp and the LED. The combined driver circuit supplies high voltage AC supply to a first portion of the driver circuit to the fluorescent lamp, supplies low voltage DC supply in a second portion of the driver circuit to the LED, and provides a secondary winding in the second portion of the driver circuit that is inductively coupled with a ballast coil in the first portion of the driver circuit that drives the fluorescent lamp.

Abstract translation: 用于驱动荧光灯和至少一个发光二极管（LED）的电路或组合镇流器包括具有交流（AC）电路的集成驱动器电路，其包括用于驱动荧光灯的至少一个镇流器线圈和直流电路 用于驱动具有与用于驱动LED的荧光灯镇流器线圈感应耦合的次级绕组的LED。 驱动灯组件的方法包括至少一个荧光灯和至少一个发光二极管（LED）和用于提供荧光灯和LED两者的组合驱动电路。 组合的驱动器电路向驱动电路的第一部分提供高压AC电源到荧光灯，将驱动电路的第二部分中的低电压DC电源提供给LED，并且在第二部分中提供次级绕组 驱动电路，其与驱动电路的驱动电路的第一部分中的镇流器线圈感应耦合。

公开(公告)号：US20090047881A1

公开(公告)日：2009-02-19

申请号：US11838653

申请日：2007-08-14

Applicant: Peter Satitpunwaycha ,  Richard Endo ,  Zachary Fresco ,  Nitin Kumar

Inventor： Peter Satitpunwaycha ,  Richard Endo ,  Zachary Fresco ,  Nitin Kumar

IPC: B24B7/04 ,  H01L21/461

CPC classification number: H01L21/67046 ,  B24B37/00 ,  C25D17/00 ,  C25D21/12 ,  H01L21/67051 ,  H01L21/68764 ,  H01L21/68785

Abstract: Combinatorial processing including rotation and movement within a region is described, including defining multiple regions of at least one substrate, processing the multiple regions of the at least one substrate in a combinatorial manner, rotating a head in one of the multiple regions to perform the processing, and repositioning the head relative to the one of the multiple regions while rotating the head during the processing.

Abstract translation: 描述包括区域内的旋转和移动的组合处理，包括限定至少一个基板的多个区域，以组合的方式处理至少一个基板的多个区域，在多个区域中的一个区域中旋转头部以执行处理 并且在处理期间旋转头部时，相对于多个区域中的一个重新定位头部。

公开(公告)号：US20090014846A1

公开(公告)日：2009-01-15

申请号：US12172110

申请日：2008-07-11

Applicant: Zachary M. Fresco ,  Chi-I Lang ,  Jinhong Tong ,  Anh Duong ,  Nitin Kumar ,  Anna Tsimelzon ,  Tony Chiang

Inventor： Zachary M. Fresco ,  Chi-I Lang ,  Jinhong Tong ,  Anh Duong ,  Nitin Kumar ,  Anna Tsimelzon ,  Tony Chiang

IPC: H01L21/312 ,  H01L29/51

CPC classification number: H01L23/5329 ,  C09D129/04 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

Abstract translation: 提出了修改图案化半导体衬底的方法，包括：提供包括电介质区域和导电区域的图案化半导体衬底表面; 以及将两亲表面改性剂施加到所述电介质区域以改变所述电介质区域。 在一些实施例中，修改电介质区域包括改变电介质区域的润湿角度。 在一些实施例中，改变润湿角度包括使介电区域的表面成为亲水性。 在一些实施方案中，方法还包括将水溶液施加到图案化的半导体衬底表面。 在一些实施例中，导电区域被水溶液选择性地增强。 在一些实施例中，方法还包括提供由低k电介质材料形成的电介质区域。 在一些实施方案中，施加两亲表面改性剂修饰低k电介质区域与随后工艺的相互作用。

公开(公告)号：US20080219039A1

公开(公告)日：2008-09-11

申请号：US11714326

申请日：2007-03-05

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Prashant B. Phatak

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US5965105A

公开(公告)日：1999-10-12

申请号：US96821

申请日：1998-06-12

Applicant: Sadhana Rayalu ,  Nitin Kumar Labhasetwar ,  Purushottam Khanna

Inventor： Sadhana Rayalu ,  Nitin Kumar Labhasetwar ,  Purushottam Khanna

IPC: C01B39/14

CPC classification number: C01B39/14 ,  Y10S423/24

Abstract: The present invention relates to a process for synthesis of flyash based Zeolite-A, said process comprising grinding and mixing of flyash and caustic soda in a ratio of 1:1.2 and optionally adding sodium aluminate or aluminium hydroxide to obtain a fine homogeneous fusion mixture; heating the said mixture in an inert vessel at about 500-600.degree. C. for about 1-2 hrs. to obtain a fused mass; cooling, milling, and mixing the said fused mass in distilled water for about 8-10 hrs. with simultaneous optional additon of sodium aluminate or alum solution, in the present or absence of NaC1 followed by optional addition of zeolite-A seeding to obtain amorphous alumino -silicate slurry; subjecting the said slurry to hydrothermal crystallisation at about 90-110.degree. C. for 2 to 4 hrs. to obtain Zeolite-A crystals; and washing the said crystals with water and then subjecting the washed crystals to oven drying at about 50-60.degree. C. to obtain the FAZ-A crystals.

Abstract translation: 本发明涉及一种合成基于飞灰的沸石-A的方法，所述方法包括以1：1.2的比例研磨和混合飞灰和苛性钠，并任选地加入铝酸钠或氢氧化铝以获得细均匀的熔融混合物; 在约500-600℃下在惰性容器中加热所述混合物约1-2小时。 得到熔融体; 冷却，研磨和将所述熔融物质在蒸馏水中混合约8-10小时。 在本发明或不存在NaCl的情况下同时选择性地添加铝酸钠或明矾溶液，然后任选加入沸石-A接种以获得无定形硅铝酸盐浆料; 将所述浆料在约90-110℃下进行水热结晶2至4小时。 得到沸石A晶体; 并用水洗涤所述晶体，然后将洗涤的晶体在约50-60℃下烘箱干燥，得到FAZ-A晶体。

公开(公告)号：US09348799B2

公开(公告)日：2016-05-24

申请号：US11484087

申请日：2006-07-10

Applicant: Nitin Kumar Garg

Inventor： Nitin Kumar Garg

IPC: G06F17/00 ,  G06F17/20 ,  G06F17/21 ,  G06F17/22 ,  G06F17/24 ,  G06F17/25 ,  G06F17/26 ,  G06F17/27 ,  G06F17/28 ,  H04N1/40 ,  H04N1/387

CPC classification number: G06F17/211 ,  G06F17/248

Abstract: Embodiments of methods, apparatuses, systems and/or devices for forming a master page for an electronic document are disclosed.

Abstract translation: 公开了用于形成用于电子文档的母版页的方法，装置，系统和/或装置的实施例。