公开(公告)号：US20050207225A1

公开(公告)日：2005-09-22

申请号：US10803183

申请日：2004-03-17

Applicant: Chiou-Feng Chen ,  Caleb Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Caleb Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC: G11C16/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC classification number: G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Abstract translation: 自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。 每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位 排列源扩散。 擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合 其他大门。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US20050207199A1

公开(公告)日：2005-09-22

申请号：US10802253

申请日：2004-03-17

Applicant: Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

Inventor： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC: G11C5/02 ,  G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115

Abstract: Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Abstract translation: 自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠 通过在单元格行的末端的选择门。 浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。 由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US5179031A

公开(公告)日：1993-01-12

申请号：US555345

申请日：1990-07-19

Applicant: Michael P. Brassington ,  Reda R. Razouk ,  Monir H. El-Diwany ,  Prateep Tuntasood

Inventor： Michael P. Brassington ,  Reda R. Razouk ,  Monir H. El-Diwany ,  Prateep Tuntasood

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L21/31116 ,  H01L21/28035 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

Abstract: A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Abstract translation: 使用单个制造工艺同时制造双极和MOS器件的方法。 在本发明的一个实施例中，硅衬底被分为双极和MOS区。 在硅衬底上热生长厚度在大约150埃至300埃范围内的薄层栅极氧化物。 厚度在大约500埃至1000埃范围内的多晶硅薄层沉积在栅极氧化物层上，以在随后的处理期间保护栅极氧化物层。 从形成发射极的双极区域去除薄多晶硅层和栅极氧化物层。 为了在蚀刻期间保持栅极氧化物层的完整性，在栅极氧化物蚀刻期间保留在多晶硅蚀刻期间使用的光致抗蚀剂掩模，并且在缓冲的氧化物溶液中蚀刻栅极氧化物。 然后将厚的多晶硅层沉积在硅衬底的双极和MOS区上，并且掩模和蚀刻衬底以形成双极和MOS器件的发射极和栅极。

公开(公告)号：US5023193A

公开(公告)日：1991-06-11

申请号：US253946

申请日：1988-10-03

Applicant: Juliana Manoliu ,  Prateep Tuntasood

Inventor： Juliana Manoliu ,  Prateep Tuntasood

IPC: H01L21/74 ,  H01L21/8249

CPC classification number: H01L21/8249 ,  H01L21/74 ,  Y10S438/911 ,  Y10S438/981

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask.

Abstract translation: 公开了同时制造双极和互补场效应晶体管的方法。 该方法包括制造掺杂有磷和砷的掩埋层18，以允许更短的扩散时间，同时提供具有低电阻和高扩散率的掩埋层。 该过程使得在接触掩模之前仅使用六个掩模制造BiCMOS结构。

公开(公告)号：US5001081A

公开(公告)日：1991-03-19

申请号：US418946

申请日：1989-10-06

Applicant: Prateep Tuntasood ,  Michael P. Brassington ,  Reda R. Razouk ,  Monir H. El-Diwany

Inventor： Prateep Tuntasood ,  Michael P. Brassington ,  Reda R. Razouk ,  Monir H. El-Diwany

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/28035 ,  H01L21/31116 ,  H01L21/8249 ,  Y10S148/009

Abstract: A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Abstract translation: 使用单个制造工艺同时制造双极和MOS器件的方法。 在本发明的一个实施例中，硅衬底被分为双极和MOS区。 在硅衬底上热生长厚度在大约150埃至300埃范围内的薄层栅极氧化物。 厚度在大约500埃至1000埃范围内的多晶硅薄层沉积在栅极氧化物层上，以在随后的处理期间保护栅极氧化物层。 从形成发射极的双极区域去除薄多晶硅层和栅极氧化物层。 为了在蚀刻期间保持栅极氧化物层的完整性，在栅极氧化物蚀刻期间保留在多晶硅蚀刻期间使用的光致抗蚀剂掩模，并且在缓冲的氧化物溶液中蚀刻栅极氧化物。 然后将厚的多晶硅层沉积在硅衬底的双极和MOS区上，并且掩模和蚀刻衬底以形成双极和MOS器件的发射极和栅极。

公开(公告)号：US4727046A

公开(公告)日：1988-02-23

申请号：US887007

申请日：1986-07-16

Applicant: Prateep Tuntasood ,  Juliana Manoliu

Inventor： Prateep Tuntasood ,  Juliana Manoliu

IPC: H01L27/092 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L29/72 ,  H01L27/04

CPC classification number: H01L27/0623 ,  H01L21/74 ,  H01L21/8249 ,  Y10S257/90

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process enables distinguishing the bipolar devices from the CMOS devices with a single base mask 108, while requiring only a single additional mask 114 to define the bipolar emitter and MOS gates. The process forms the gate oxide 100 for the MOS devices at an early stage, then protects that oxide with polysilicon 103 during subsequent fabrication steps. Self-aligned metal silicide contacts 137 are separated from undesired regions using sidewall oxidation techniques.

公开(公告)号：US07646641B2

公开(公告)日：2010-01-12

申请号：US10869475

申请日：2004-06-15

Applicant: Chiou-Feng Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568

Abstract: NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

Abstract translation: NAND闪速存储单元阵列具有控制栅极和电荷存储门，它们成对地排列成位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。 每个堆叠对中的栅极彼此自对准，并且电荷存储栅极是氮化物或氮化物和氧化物的组合。 通过从硅衬底到电荷存储门的热电子注入来完成编程，以在电荷存储门中建立负电荷。 通过从电荷存储栅极到硅衬底的沟道隧穿或通过从硅衬底到电荷存储栅的热空穴注入来完成擦除。 该阵列被偏置，使得所有的存储单元可以同时被擦除，而编程是位可选择的。

公开(公告)号：US20090201744A1

公开(公告)日：2009-08-13

申请号：US12027654

申请日：2008-02-07

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US07501321B2

公开(公告)日：2009-03-10

申请号：US11535694

申请日：2006-09-27

Applicant: Prateep Tuntasood ,  Der-Tsyr Fan ,  Chiou-Feng Chen

Inventor： Prateep Tuntasood ,  Der-Tsyr Fan ,  Chiou-Feng Chen

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

Abstract: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

Abstract translation: NAND闪存单元阵列和具有存储器栅极和电荷存储层的单元被密集地堆叠的制造工艺，相邻单元中的存储器栅彼此重叠或自对准。 存储器单元在位线扩散和公共源极扩散之间排成行，电荷存储层位于单元中的存储器栅极下方。 存储器栅极是多晶硅或多晶硅，并且电荷存储栅极是氮化物或氮化物和氧化物的组合。 通过从硅衬底到电荷存储门的热电子注入来完成编程，以在电荷存储门中建立负电荷，或通过从硅衬底到电荷存储门的热空穴注入，以在电荷中建立正电荷 存储门 根据编程方法，通过从电荷存储门到硅衬底的沟道隧道进行擦除，反之亦然。 该阵列被偏置，使得所有的存储单元可以同时被擦除，而编程是位可选择的。

公开(公告)号：US20070032018A1

公开(公告)日：2007-02-08

申请号：US11535694

申请日：2006-09-27

Applicant: Prateep Tuntasood ,  Der-Tsyr Fan ,  Chiou-Feng Chen

Inventor： Prateep Tuntasood ,  Der-Tsyr Fan ,  Chiou-Feng Chen

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

Abstract: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

Abstract translation: NAND闪存单元阵列和具有存储器栅极和电荷存储层的单元被密集地堆叠的制造工艺，相邻单元中的存储器栅彼此重叠或自对准。 存储器单元在位线扩散和公共源极扩散之间排成行，电荷存储层位于单元中的存储器栅极下方。 存储器栅极是多晶硅或多晶硅，并且电荷存储栅极是氮化物或氮化物和氧化物的组合。 通过从硅衬底到电荷存储门的热电子注入来完成编程，以在电荷存储门中建立负电荷，或通过从硅衬底到电荷存储门的热空穴注入，以在电荷中建立正电荷 存储门 根据编程方法，通过从电荷存储门到硅衬底的沟道隧道进行擦除，反之亦然。 该阵列被偏置，使得所有的存储单元可以同时被擦除，而编程是位可选择的。