公开(公告)号：US20240421166A1

公开(公告)日：2024-12-19

申请号：US18641596

申请日：2024-04-22

Applicant: Renesas Electronics Corporation

Inventor： Makoto KOSHIMIZU ,  Shigeki TSUBAKI

IPC: H01L27/144 ,  H01L21/762 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L31/02

Abstract: An anode region and a cathode region of a photodiode are formed in a semiconductor substrate. At a main surface of the semiconductor substrate, a plurality of first STI regions are formed on the cathode region, and an oxide film is formed between the plurality of first STI regions. A shield electrode is formed on the plurality of first STI regions and the oxide film. A thickness of each of the plurality of first STI regions is smaller than a thickness of second STI region.

公开(公告)号：US12160245B2

公开(公告)日：2024-12-03

申请号：US17188247

申请日：2021-03-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaaki Usui

IPC: H03M1/12 ,  G06F11/07 ,  H03M1/10

Abstract: An AD converter includes a plurality of analog input terminals, a reference signal generation circuit that generates an analog reference signal, a sample-and-hold unit that includes a plurality of sample-and-hold circuits sampling the analog reference signal or one of analog input signals from the analog input terminals, a control unit that controls the sample-and-hold unit, and a conversion unit that converts an output signal from the sample-and-hold unit into a digital signal. The control unit controls the sample-and-hold unit to perform the output operation for analog input signal and the sampling operation for the analog reference signal.

公开(公告)号：US12159934B2

公开(公告)日：2024-12-03

申请号：US17722788

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi Eikyu ,  Atsushi Sakai ,  Yotaro Goto

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

公开(公告)号：US20240395823A1

公开(公告)日：2024-11-28

申请号：US18795310

申请日：2024-08-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20240372640A1

公开(公告)日：2024-11-07

申请号：US18635469

申请日：2024-04-15

Applicant: Renesas Electronics Corporation

Inventor： Christian MARDMÖLLER ,  Mohamed SOUBHI ,  Stefan GELDREICH

IPC: H04J3/06 ,  H04L1/00 ,  H04L67/12

Abstract: The present document relates to a processing device and a method for performing time stamping of data at a high level of integrity such as ASIL (Automotive Safety Integrity Level) D. The processing device processes a data frame comprising data. Furthermore, upon reception of a trigger which is indicative of the processing of the data frame, the processing device captures a time stamp using a primary timer. Next, the processing device generates validation data based on the data frame and the time stamp. In addition, the processing device stores the validation data in conjunction with the data frame and the time stamp in a memory module.

公开(公告)号：US12136931B2

公开(公告)日：2024-11-05

申请号：US17983576

申请日：2022-11-09

Applicant: Renesas Electronics Corporation

Inventor： Pratama Fajarmega ,  Tatsuo Nishino ,  Takehiro Shimizu

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/10 ,  H03M1/38 ,  H03M1/76

Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.

公开(公告)号：US20240363750A1

公开(公告)日：2024-10-31

申请号：US18771200

申请日：2024-07-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

CPC classification number: H01L29/7838 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H03F3/45179

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20240363747A1

公开(公告)日：2024-10-31

申请号：US18603396

申请日：2024-03-13

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/1095

Abstract: The semiconductor device includes a pair of gate-electrodes GE formed inside the pair of trenches TR via an gate insulating film (GI), respectively. The pair of column regions PC are spaced apart from each other in the Y-direction. The pair of trenches TR are provided apart from each other in the Y direction, are provided between the pair of column regions PC in the Y direction, and extend in the X direction. The ends of the pair of trenches TR in the X direction are connected to each other by a connecting portion TRa extending in the Y direction. The connection portion TRa is integrated with the pair of trenches TR. The pair of column regions PC extend in the X direction along the pair of trenches TR, and extend in the X direction toward the outer edge of the semiconductor substrate beyond the connection portion TRa.

公开(公告)号：US20240349509A1

公开(公告)日：2024-10-17

申请号：US18595236

申请日：2024-03-04

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H10B51/30 ,  H01L21/28 ,  H01L29/51

CPC classification number: H10B51/30 ,  H01L29/40111 ,  H01L29/516

Abstract: A performance of a semiconductor device is improved. A gate insulating film is formed on a semiconductor substrate. A gate electrode is formed on the gate insulating film. A ferroelectric film and a metal film are formed between the gate insulating film and the gate electrode. A thickness of the metal film is smaller than a thickness of the ferroelectric film. The metal film is amorphous.

公开(公告)号：US20240312950A1

公开(公告)日：2024-09-19

申请号：US18439249

申请日：2024-02-12

Applicant: Renesas Electronics Corporation

Inventor： Takaya HOSHI ,  Fumiaki AGA

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/49 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/49051 ,  H01L2224/49052 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2924/386

Abstract: A plurality of wires of a semiconductor device includes: a first wire connected to each of an end portion electrode and a first terminal of a plurality of terminals; and a second wire connected to each of a non-end portion electrode and a second terminal of the plurality of terminals. A loop height of the first wire is greater than a loop height of the second wire.