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61 条记录 (耗时 0.017 秒)

    HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE
    21.
    发明申请
    HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE 有权
    高性能低功率散热FET器件及其制造方法

    公开(公告)号：US20120056275A1

    公开(公告)日：2012-03-08

    申请号：US12876480

    申请日：2010-09-07

    申请人： Jin CAI ,  Toshiharu FURUKAWA ,  Robert R. ROBISON

    发明人： Jin CAI ,  Toshiharu FURUKAWA ,  Robert R. ROBISON

    IPC分类号： H01L29/772 ,  H01L21/335

    CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

    摘要： A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.

    摘要翻译： 形成半导体器件的方法包括：在衬底中形成场效应晶体管（FET）的沟道; 在衬底中形成重掺杂区域; 以及形成与沟道和重掺杂区相邻的凹槽。 该方法还包括：在通道和重掺杂区域的暴露部分上的凹槽中形成未掺杂或轻掺杂的中间层; 以及在中间层上形成源极和漏极区域，使得源极和漏极区域通过中间层与重掺杂区域间隔开。

    Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure
    22.
    发明授权
    Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure 有权
    结合了多个氮化物层以提高远离器件的散热的半导体结构和形成该结构的方法

    公开(公告)号：US08053870B2

    公开(公告)日：2011-11-08

    申请号：US12638004

    申请日：2009-12-15

    申请人： Brent A. Anderson ,  Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison

    发明人： Brent A. Anderson ,  Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L23/58

    CPC分类号： H01L23/53295 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L2224/18

    摘要： Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer). Optionally, the embodiments also incorporate incomplete contacts that extend through the blanket oxide layer into one or more of the nitride layers without contacting the device in order to further improve heat dissipation.

    摘要翻译： 公开了一种半导体结构的实施例，该半导体结构包括层叠在器件的中心区域和覆盖氧化物层之间的多个氮化物层。 这些氮化物层比覆盖氧化物层更具有导热性，因此提供远离器件的改进的散热。 还公开了在其它器件的标准处理期间结合形成下列氮化物层的方法的一种方法的实施例：氮化物硬掩模层（OP层），“牺牲”氮化物层（SMT层 ），拉伸氮化物层（WN层）和/或压缩氮化物层（WP层）。 可选地，实施例还包括不完全接触，其将覆盖氧化物层延伸到一个或多个氮化物层中，而不接触该器件，以进一步改善散热。

    STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
    23.
    发明申请
    STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES 有权
    用于制造不对称装置的结构和方法

    公开(公告)号：US20110254059A1

    公开(公告)日：2011-10-20

    申请号：US13167303

    申请日：2011-06-23

    申请人： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

    发明人： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

    IPC分类号： H01L29/808 ,  H01L21/337 ,  B82Y99/00

    CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

    摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

    摘要翻译： 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

    Use of contacts to create differential stresses on devices
    27.
    发明授权
    Use of contacts to create differential stresses on devices 有权
    使用触点在器件上产生差分应力

    公开(公告)号：US08815671B2

    公开(公告)日：2014-08-26

    申请号：US12892474

    申请日：2010-09-28

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

    摘要翻译： 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。 本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。 在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。 在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

    Butted SOI junction isolation structures and devices and method of fabrication
    28.
    发明授权
    Butted SOI junction isolation structures and devices and method of fabrication 有权
    对接SOI结隔离结构和器件及其制造方法

    公开(公告)号：US08741725B2

    公开(公告)日：2014-06-03

    申请号：US12943084

    申请日：2010-11-10

    申请人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

    发明人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

    摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

    摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。