公开(公告)号：US08625242B2

公开(公告)日：2014-01-07

申请号：US13197136

申请日：2011-08-03

Applicant: Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

Inventor： Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

IPC: H02H3/20

CPC classification number: H04L25/0266 ,  H01F27/40 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A system includes a transmitter, a receiver, a isolation barrier, and a fuse. The isolation barrier is connected to the transmitter. The fuse is connected between the isolation barrier and the receiver. The isolation barrier prevents current flow from the transmitter to the receiver when a voltage across the isolation barrier is less than a first breakdown voltage. The isolation barrier short circuits when the voltage across the isolation barrier is greater than or equal to the first breakdown voltage. The fuse opens when the isolation barrier short circuits. When open, the fuse has a second breakdown voltage that is greater than the first breakdown voltage.

Abstract translation: 系统包括发射机，接收机，隔离屏障和保险丝。 隔离屏障连接到变送器。 保险丝连接在隔离屏障和接收器之间。 当隔离隔离层上的电压小于第一击穿电压时，隔离屏障防止电流从发射器流向接收器。 当隔离屏障上的电压大于或等于第一击穿电压时，隔离栅短路。 保险丝断开时隔离屏障短路。 当断开时，保险丝的第二击穿电压大于第一击穿电压。

公开(公告)号：US20130033791A1

公开(公告)日：2013-02-07

申请号：US13197136

申请日：2011-08-03

Applicant: Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

Inventor： Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

IPC: H02H3/20 ,  H02H3/24

CPC classification number: H04L25/0266 ,  H01F27/40 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A system includes a transmitter, a receiver, a isolation barrier, and a fuse. The isolation barrier is connected to the transmitter. The fuse is connected between the isolation barrier and the receiver. The isolation barrier prevents current flow from the transmitter to the receiver when a voltage across the isolation barrier is less than a first breakdown voltage. The isolation barrier short circuits when the voltage across the isolation barrier is greater than or equal to the first breakdown voltage. The fuse opens when the isolation barrier short circuits. When open, the fuse has a second breakdown voltage that is greater than the first breakdown voltage.

Abstract translation: 系统包括发射机，接收机，隔离屏障和保险丝。 隔离屏障连接到变送器。 保险丝连接在隔离屏障和接收器之间。 当隔离隔离层上的电压小于第一击穿电压时，隔离屏障防止电流从发射器流向接收器。 当隔离屏障上的电压大于或等于第一击穿电压时，隔离栅短路。 保险丝断开时隔离屏障短路。 当断开时，保险丝的第二击穿电压大于第一击穿电压。

公开(公告)号：US20110169509A1

公开(公告)日：2011-07-14

申请号：US12685992

申请日：2010-01-12

Applicant: Roberto Alini ,  Roberto Casiraghi

Inventor： Roberto Alini ,  Roberto Casiraghi

IPC: G01R27/26

CPC classification number: G03B21/53 ,  G01R27/2605 ,  G02B7/08 ,  G03B3/10 ,  G03B13/34

Abstract: A driver and capacitance measuring circuit includes a voltage source that selectively generates an output voltage at a first node during a driver mode to alter a capacitance of a device that is connected to the first node and that has a variable capacitance. A current source selectively provides one of a charging and discharging current at the first node during a measurement mode. A capacitance calculating circuit samples a voltage at the first node during the measurement node, determines a voltage change rate of the first node during the measurement mode and calculates the capacitance of the device based on the voltage change rate and a value of the one of the charging and discharging current.

Abstract translation: 驱动器和电容测量电路包括电压源，其在驱动器模式期间选择性地在第一节点处产生输出电压，以改变连接到第一节点并具有可变电容的装置的电容。 在测量模式期间，电流源选择性地提供第一节点处的充电和放电电流之一。 电容计算电路在测量节点期间对第一节点处的电压进行采样，在测量模式期间确定第一节点的电压变化率，并基于电压变化率和电压变化率的一个值计算器件的电容 充放电电流。

公开(公告)号：US06512649B1

公开(公告)日：2003-01-28

申请号：US09651830

申请日：2000-08-30

Applicant: Roberto Alini ,  Quocdzung T. Lam ,  Xiaokun Liu Chew ,  Mark McCornack ,  David Joseph Bezinque ,  Tehri Lee ,  Su Dang Le ,  Axel Alegre de La Soujeole ,  Gilles Denoyer

Inventor： Roberto Alini ,  Quocdzung T. Lam ,  Xiaokun Liu Chew ,  Mark McCornack ,  David Joseph Bezinque ,  Tehri Lee ,  Su Dang Le ,  Axel Alegre de La Soujeole ,  Gilles Denoyer

IPC: G11B502

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B5/40 ,  G11B2005/001 ,  G11B2005/0013

Abstract: A method is disclosed for controlling the write head of a magnetic disk storage device. The method includes sinking current from the first terminal of the write head and sourcing current to the second terminal of the write head substantially simultaneously with sinking current from the first terminal so that a first steady state voltage level appears on the first terminal of the write head and a second steady state voltage level appears on the second terminal thereof that are approximately at a midpoint between a high reference voltage level and a low reference voltage level. The common mode voltage of the write head is substantially constant over time.

Abstract translation: 公开了一种用于控制磁盘存储装置的写入头的方法。 该方法包括从写入头的第一端子吸收电流并且将源电流基本上与来自第一端子的电流进行同时地馈送到写入头的第二端子，使得第一稳态电压电平出现在写入头的第一端上 并且第二稳态电压电平出现在其第二端上，其大约在高参考电压电平和低参考电压电平之间的中点。 写入头的共模电压随时间基本上是恒定的。

公开(公告)号：US06473251B2

公开(公告)日：2002-10-29

申请号：US09398609

申请日：1999-09-17

Applicant: Giuseppe Patti ,  Gilles Denoyer ,  Roberto Alini

Inventor： Giuseppe Patti ,  Gilles Denoyer ,  Roberto Alini

IPC: G11B502

CPC classification number: G11B5/012 ,  G11B2005/0016

Abstract: An apparatus (and method) is provided that reduces thermal interference in the read signal of a disk drive. A variable or programmable resistance is used to change the transfer function of a filter in the read channel of the disk drive to filter the read signal. The filter has a first transfer function (first cut-off frequency) related to the programmed resistance during normal operation of the disk drive (i.e. when thermal interference is not detected). When thermal interference is detected in the read signal, the resistance is programmed to another value resulting in the filter having a second transfer function (second cut-off frequency). The resistance element includes a transconductance amplifier whose transconductance is variable or programmable to different values resulting in different programmable transfer functions (or one of a multitude of cut-off frequencies) for the filter. In the preferred embodiment, detection of thermal interference increases the cut-off frequency of the filter thereby filtering, or reducing the effects of, the thermal interference in the read signal.

Abstract translation: 提供了减少磁盘驱动器的读取信号中的热干扰的装置（和方法）。 使用可变或可编​​程电阻来改变磁盘驱动器的读通道中的滤波器的传递函数，以过滤读取信号。 滤波器在磁盘驱动器的正常操作期间（即，当未检测到热干扰时）具有与编程电阻相关的第一传递函数（第一截止频率）。 当在读取信号中检测到热干扰时，电阻被编程为另一个值，导致滤波器具有第二传递函数（第二截止频率）。 电阻元件包括跨导放大器，其跨导是可变的或可编程为不同的值，导致滤波器的不同的可编程传递函数（或多个截止频率之一）。 在优选实施例中，热干扰的检测增加了滤波器的截止频率，从而过滤或减少了读取信号中的热干扰的影响。

公开(公告)号：US5912582A

公开(公告)日：1999-06-15

申请号：US866889

申请日：1997-05-30

Applicant: Valerio Pisati ,  Roberto Alini ,  Gaetano Cosentino ,  Gianfranco Vai

Inventor： Valerio Pisati ,  Roberto Alini ,  Gaetano Cosentino ,  Gianfranco Vai

IPC: H03F3/45 ,  H03F3/72 ,  H03B1/00 ,  H03K5/00 ,  H04B1/10

CPC classification number: H03F3/72 ,  H03F3/45286 ,  H03F2203/45302 ,  H03F2203/45304 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45506

Abstract: A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor. In a variant differential stage, there are also provided respective added MOS transistors connected in parallel with the MOS transistors of the input circuit portion to change the ratio W:L of each of the MOS transistors.

Abstract translation: 用于高频滤波器的BiCMOS跨导差分级包括具有信号输入的输入电路部分和具有对应于信号输入的各自的栅极端子的一对MOS晶体管。 差分级具有具有信号输出的输出电路部分和一对双极晶体管，它们以共模基极连接在共模基底上，该公共基极以共源共栅配置插入在输入端和输出端之间。 差分级包括与双极晶体管中的至少一个相关联的开关器件，以改变差分级中存在的寄生电容器之间的连接。 开关器件还具有至少一个加法双极晶体管，其以可移除的方式与相应的双极共源共栅晶体管并联连接。 在变异差分级中，还提供了与输入电路部分的MOS晶体管并联连接的各个附加的MOS晶体管，以改变每个MOS晶体管的比率W：L。

公开(公告)号：US5521598A

公开(公告)日：1996-05-28

申请号：US285842

申请日：1994-08-04

Applicant: David Moloney ,  Paolo Gadducci ,  Marco Demicheli ,  Roberto Alini

Inventor： David Moloney ,  Paolo Gadducci ,  Marco Demicheli ,  Roberto Alini

IPC: G06F3/06 ,  G11B20/10 ,  G11B20/14 ,  H03M5/14 ,  H03M7/00

CPC classification number: H03M5/145 ,  G11B20/1426

Abstract: A decoder of a coded serial stream of digital data in a stream of decoded NRZ data has re-timing (BB, AA) flip-flops and a 2.times.1 multiplexer (MUX OUT) selectably providing a single-bit NRZ output stream or a dual-bit (NRZ0 and NRZ1) output streams, by exploiting the predecoded values (ND0 and ND1) produced by two decoding combinative logic networks (RC1 and RC2) that compose the decoder.

Abstract translation: 解码的NRZ数据流中的数字数据编码串行数据流的解码器具有重新定时（BB，AA）触发器和可选择地提供单位NRZ输出流或双倍数位NRZ输出流的2×1多路复用器（MUX OUT） （NRZ0和NRZ1）输出流，通过利用组成解码器的两个解码组合逻辑网络（RC1和RC2）产生的预解码值（ND0和ND1）。

公开(公告)号：US5430337A

公开(公告)日：1995-07-04

申请号：US105736

申请日：1993-08-12

Applicant: Rinaldo Castello ,  Roberto Alini ,  Francesco Rezzi ,  Valerio Pisati

Inventor： Rinaldo Castello ,  Roberto Alini ,  Francesco Rezzi ,  Valerio Pisati

IPC: H03F1/32 ,  H03F3/45 ,  H03H11/04 ,  H03K17/60 ,  G06G7/12

CPC classification number: H03F1/3211 ,  H03F3/45076 ,  H03F3/45282

Abstract: A transconductor stage for high-frequency filters of a type which comprises an input circuit portion having signal inputs and an output circuit portion, incorporates a pair of field-effect transistors having respective gate and source terminals in common, and has the output portion formed of a pair of bipolar transistors connected to the aforesaid field-effect transistors.

Abstract translation: 一种用于包括具有信号输入的输入电路部分和输出电路部分的类型的高频滤波器的跨导级，包括一对共同具有各自的栅极和源极端子的场效应晶体管，并且具有由 连接到上述场效应晶体管的一对双极晶体管。

公开(公告)号：US08890368B2

公开(公告)日：2014-11-18

申请号：US13169364

申请日：2011-06-27

Applicant: Baris Posat ,  Roberto Alini

Inventor： Baris Posat ,  Roberto Alini

IPC: H01F27/42 ,  H01F37/00 ,  H01F38/00 ,  H02M3/335 ,  H02J5/00 ,  H01L23/522 ,  H01L23/64 ,  H01L23/495 ,  H01F19/08

CPC classification number: H01F38/14 ,  H01F2019/085 ,  H01L23/495 ,  H01L23/5227 ,  H01L23/645 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/30107 ,  H02J5/005 ,  H02J50/12 ,  H02J50/80 ,  H01L2924/00

Abstract: An integrated circuit (IC) includes first and second resonator circuits and an isolation barrier. The first resonator circuit includes first and second inductors, wherein the first resonator circuit is connected to a supply voltage. The second resonator circuit includes third and fourth inductors, wherein the second resonator circuit is matched to the first resonator circuit. The isolation barrier separates the first and second resonator circuits. The first and second inductors are inductively coupled to the third and fourth inductors, respectively, thereby providing for transfer of power from the first resonator circuit across the isolation barrier to the second resonator circuit.

Abstract translation: 集成电路（IC）包括第一和第二谐振器电路和隔离屏障。 第一谐振器电路包括第一和第二电感器，其中第一谐振器电路连接到电源电压。 第二谐振器电路包括第三和第四电感器，其中第二谐振器电路与第一谐振器电路匹配。 隔离栅分离第一和第二谐振器电路。 第一和第二电感器分别感应耦合到第三和第四电感器，从而提供从第一谐振器电路跨越隔离屏障到第二谐振器电路的功率传递。

公开(公告)号：US20120326773A1

公开(公告)日：2012-12-27

申请号：US13169364

申请日：2011-06-27

Applicant: Baris Posat ,  Roberto Alini

Inventor： Baris Posat ,  Roberto Alini

IPC: H03K5/00

CPC classification number: H01F38/14 ,  H01F2019/085 ,  H01L23/495 ,  H01L23/5227 ,  H01L23/645 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/30107 ,  H02J5/005 ,  H02J50/12 ,  H02J50/80 ,  H01L2924/00

Abstract: An integrated circuit (IC) includes first and second resonator circuits and an isolation barrier. The first resonator circuit includes first and second inductors, wherein the first resonator circuit is connected to a supply voltage. The second resonator circuit includes third and fourth inductors, wherein the second resonator circuit is matched to the first resonator circuit. The isolation barrier separates the first and second resonator circuits. The first and second inductors are inductively coupled to the third and fourth inductors, respectively, thereby providing for transfer of power from the first resonator circuit across the isolation barrier to the second resonator circuit.

Abstract translation: 集成电路（IC）包括第一和第二谐振器电路和隔离屏障。 第一谐振器电路包括第一和第二电感器，其中第一谐振器电路连接到电源电压。 第二谐振器电路包括第三和第四电感器，其中第二谐振器电路与第一谐振器电路匹配。 隔离栅分离第一和第二谐振器电路。 第一和第二电感器分别电感耦合到第三和第四电感器，从而提供从第一谐振器电路跨越隔离屏障到第二谐振器电路的功率传递。