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81 条记录 (耗时 0.028 秒)

    SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME
    21.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME 失效
    半导体存储器件及其相关方法

    公开(公告)号：US20080253213A1

    公开(公告)日：2008-10-16

    申请号：US12145876

    申请日：2008-06-25

    申请人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

    发明人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

    IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C5/14

    CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4068

    摘要： A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

    摘要翻译： 用于半导体存储器件的刷新方法具有高抗噪声性，更低的功耗和更低的成本。 在自刷新模式中未被选择的一个或多个存储单元块的所有字线被控制为具有基本上处于地平面的浮动电位。 即使当字线和位线短路时，该控制也可以防止可能由噪声引起的存储单元信息的破坏，并且还防止漏电流的产生。 不需要用于防止产生泄漏电流的保险丝等，从而实现较低的成本。

    Method of manufacturing electron emission source
    22.
    发明授权
    Method of manufacturing electron emission source 失效
    制造电子发射源的方法

    公开(公告)号：US07399214B2

    公开(公告)日：2008-07-15

    申请号：US11416319

    申请日：2006-05-03

    申请人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

    发明人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

    IPC分类号： H01J9/24

    CPC分类号： H01J9/025 ,  B82Y10/00 ,  H01J31/127 ,  H01J2201/30469

    摘要： The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.

    摘要翻译： 在绝缘层中形成露出碳纳米管层的开口的步骤是在条件下使用彼此不同的两种类型的干蚀刻进行的。 在第一级干蚀刻步骤中，在绝缘层中形成一个不暴露碳纳米管层的深度的孔。 此后，在第二阶段干蚀刻步骤中，去除孔的底表面部分，从而暴露碳纳米管层的上表面。 由此可以得到能够提高电子发射部的性能的电子发射源的制造方法。

    Semiconductor memory device and method of controlling the semiconductor memory device
    24.
    发明申请
    Semiconductor memory device and method of controlling the semiconductor memory device 失效
    半导体存储器件和控制半导体存储器件的方法

    公开(公告)号：US20070237014A1

    公开(公告)日：2007-10-11

    申请号：US11806721

    申请日：2007-06-04

    申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

    摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

    摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

    Non-volatile memory device and erasing method therefor
    25.
    发明授权
    Non-volatile memory device and erasing method therefor 有权
    非易失性存储器件及其擦除方法

    公开(公告)号：US07266019B2

    公开(公告)日：2007-09-04

    申请号：US11215889

    申请日：2005-08-30

    申请人： Hideho Taoka ,  Yoshihiro Suzumura ,  Kanji Hirano ,  Satoru Kawamoto

    发明人： Hideho Taoka ,  Yoshihiro Suzumura ,  Kanji Hirano ,  Satoru Kawamoto

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/107 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3468 ,  G11C2216/18

    摘要： During an erasing sequence, after a preprogram operation (S1), an erasing operation (S3), and an APDE operation (S5) are executed and confirmation by an APDE verify operation (S6: P) and confirmation by an erase-verify operation (S7: P) are completed, step A is executed prior to a soft-program operation (S10) of a plurality of memory cells. A dummy memory cell program operation (S8) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S9). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S11) can be prevented, and excessive soft-programming can be avoided.

    摘要翻译： 在擦除顺序期间，在预编程操作（S1）之后，执行擦除操作（S 3）和APDE操作（S 5）并通过APDE验证操作（S 6：P）进行确认并通过擦除确认 （S 7：P）完成时，在多个存储单元的软编程操作（S10）之前执行步骤A. 连续执行虚拟存储器单元编程操作（S 8），直到通过虚拟存储器单元程序验证操作确认完成编程操作（S 9）。 通过对虚拟存储单元执行程序操作，通过位线将与程序操作类似的电压应力施加于过擦除状态的存储单元。 因此，过擦除状态被降低，从而降低列泄漏电流。 可以防止在软程序验证操作期间的错误识别（S11），并且可以避免过多的软编程。

    Method of manufacturing electron emission source
    26.
    发明申请
    Method of manufacturing electron emission source 失效
    制造电子发射源的方法

    公开(公告)号：US20060258254A1

    公开(公告)日：2006-11-16

    申请号：US11416319

    申请日：2006-05-03

    申请人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

    发明人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

    IPC分类号： H01J9/04

    CPC分类号： H01J9/025 ,  B82Y10/00 ,  H01J31/127 ,  H01J2201/30469

    摘要： The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.

    摘要翻译： 在绝缘层中形成露出碳纳米管层的开口的步骤是在条件下使用彼此不同的两种类型的干蚀刻进行的。 在第一级干蚀刻步骤中，在绝缘层中形成一个不暴露碳纳米管层的深度的孔。 此后，在第二阶段干蚀刻步骤中，去除孔的底表面部分，从而暴露碳纳米管层的上表面。 由此可以得到能够提高电子发射部的性能的电子发射源的制造方法。

    Current-voltage converter circuit and its control method
    29.
    发明申请
    Current-voltage converter circuit and its control method 有权
    电流 - 电压转换电路及其控制方法

    公开(公告)号：US20050184767A1

    公开(公告)日：2005-08-25

    申请号：US11061119

    申请日：2005-02-18

    申请人： Kenji Shibata ,  Satoru Kawamoto

    发明人： Kenji Shibata ,  Satoru Kawamoto

    IPC分类号： G11C16/26 ,  G11C16/28 ,  H03D1/00

    CPC分类号： G11C16/28

    摘要： An input current flowing into a current-voltage conversion circuit (1) is converted to a voltage value at an output terminal SAIN and, then, a differential amplification circuit (5) amplifies and outputs a differential voltage between the voltage value and the reference voltage Vref. PMOS and NMOS transistors T1, T2 are connected between the output terminal SAIN and the power-supply voltage VCC. After the output terminal SAIN is precharged to the power-supply voltage VCC by making the transistors conductive, the current-voltage conversion operation is performed by making a voltage drop corresponding to the input current. The precharge operation precharges the output terminal SAIN up to the power-supply voltage VCC and supplies precharge to a common data line N3 and bit lines.

    摘要翻译： 流入电流 - 电压转换电路（1）的输入电流被转换为输出端子SAIN处的电压值，然后差分放大电路（5）放大并输出电压值与基准电压之间的差分电压 Vref。 PMOS和NMOS晶体管T 1，T 2连接在输出端子SAIN和电源电压VCC之间。 在通过使晶体管导通来将输出端子SAIN预充电到电源电压VCC之后，通过使与输入电流相对应的电压降来执行电流 - 电压转换操作。 预充电操作将输出端子SAIN预充电到电源电压VCC，并将预充电提供给公共数据线N 3和位线。