公开(公告)号：US07399214B2

公开(公告)日：2008-07-15

申请号：US11416319

申请日：2006-05-03

申请人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

发明人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

IPC分类号： H01J9/24

CPC分类号： H01J9/025 ,  B82Y10/00 ,  H01J31/127 ,  H01J2201/30469

摘要： The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.

摘要翻译： 在绝缘层中形成露出碳纳米管层的开口的步骤是在条件下使用彼此不同的两种类型的干蚀刻进行的。 在第一级干蚀刻步骤中，在绝缘层中形成一个不暴露碳纳米管层的深度的孔。 此后，在第二阶段干蚀刻步骤中，去除孔的底表面部分，从而暴露碳纳米管层的上表面。 由此可以得到能够提高电子发射部的性能的电子发射源的制造方法。

公开(公告)号：US20060258254A1

公开(公告)日：2006-11-16

申请号：US11416319

申请日：2006-05-03

申请人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

发明人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

IPC分类号： H01J9/04

CPC分类号： H01J9/025 ,  B82Y10/00 ,  H01J31/127 ,  H01J2201/30469

摘要： The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.

摘要翻译： 在绝缘层中形成露出碳纳米管层的开口的步骤是在条件下使用彼此不同的两种类型的干蚀刻进行的。 在第一级干蚀刻步骤中，在绝缘层中形成一个不暴露碳纳米管层的深度的孔。 此后，在第二阶段干蚀刻步骤中，去除孔的底表面部分，从而暴露碳纳米管层的上表面。 由此可以得到能够提高电子发射部的性能的电子发射源的制造方法。

公开(公告)号：US07514781B2

公开(公告)日：2009-04-07

申请号：US11602230

申请日：2006-11-21

申请人： Satoru Kawamoto

发明人： Satoru Kawamoto

IPC分类号： H01L23/14

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0366 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/029 ,  Y10T428/24917 ,  H01L2924/00

摘要： A circuit substrate includes a plurality of dielectric members and a plurality of wiring patterns. The plurality of wiring patterns are stacked on one another through the plurality of dielectric members. The plurality of dielectric members includes a mount dielectric member. A first wiring pattern of the plurality of wiring patterns is provided on a side of the mount dielectric member. A second wiring pattern of the plurality of wiring patterns is provided on an opposite side of the mount dielectric member. A first length is a length between a reinforcing medium of the mount dielectric member and the opposite side of the mount dielectric member in a thickness direction. A second length is a length between the reinforcing medium of the mount dielectric member and the side of the mount dielectric member in the thickness direction. The first length is smaller than the second length.

摘要翻译： 电路基板包括多个电介质构件和多个布线图案。 多个布线图案通过多个电介质构件彼此堆叠。 多个电介质构件包括安装电介质构件。 多个布线图案的第一布线图案设置在安装电介质构件的一侧。 多个布线图案的第二布线图案设置在安装电介质构件的相对侧上。 第一长度是在安装电介质构件的加强介质和安装电介质构件的厚度方向的相对侧之间的长度。 第二长度是在安装电介质构件的加强介质和安装电介质构件的厚度方向的一侧之间的长度。 第一长度小于第二长度。

公开(公告)号：US07358778B2

公开(公告)日：2008-04-15

申请号：US11482129

申请日：2006-07-07

申请人： Kenta Kato ,  Satoru Kawamoto

发明人： Kenta Kato ,  Satoru Kawamoto

IPC分类号： H03K5/22 ,  H03K5/153

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/143 ,  G11C16/30

摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

摘要翻译： 一种电压检测电路，用于在抑制由晶体管的漏电流引起的电压波动的同时精确地检测电压。 电压检测电路包括第一和第二电容器，第一和第二晶体管，比较器和控制电路。 电容器串联连接以产生对应于电容器的高电压的分压。 当晶体管被激活时，第一电容器和第二电容器之间的节点处的电位被复位为接地电位。 当节点处的电位达到预定电位时，第一晶体管失活，然后第二晶体管失活。

公开(公告)号：US20070222531A1

公开(公告)日：2007-09-27

申请号：US11802637

申请日：2007-05-24

申请人： Yasushige Ogawa ,  Satoru Kawamoto

发明人： Yasushige Ogawa ,  Satoru Kawamoto

IPC分类号： H03B5/04

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067 ,  H03K3/012 ,  H03K3/014 ,  H03K3/0315 ,  H03K5/1252 ,  H03K5/19 ,  H03L3/00

摘要： There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).

摘要翻译： 提供了一种振荡器电路，其能够通过在振荡开始时避免可能发生在操作/停止控制可行型振荡器电路的频率不稳定的输出而获得稳定的频率。 在这种振荡电路中，振荡允许信号（EN）将振荡器部分置于振荡可操作状态，由此控制器部分开始工作。 已经看到其操作的控制器部分将振荡频率控制信号（VR）改变成对应于预定振荡频率的信号值，以便在振荡器部分设置振荡频率。 此外，振荡器部分响应于在检测器部分将输入的信号与预定信号值进行比较之后输出的检测信号（MON）输出振荡信号，并检测输入信号达到预定信号值。 由此，可以检测振荡频率控制信号（VR）的瞬态。 也就是说，可以避免由于瞬态振荡频率控制信号（VR）引起的不稳定振荡​​信号的输出。

公开(公告)号：US20070076492A1

公开(公告)日：2007-04-05

申请号：US11529790

申请日：2006-09-29

申请人： Hideki Arakawa ,  Satoru Kawamoto

发明人： Hideki Arakawa ,  Satoru Kawamoto

IPC分类号： G11C7/00

CPC分类号： G11C5/145

摘要： A storage device and its control method are described, according to which a bias voltage to be supplied to a memory cell array is selected from boosted voltages which are increased from an external voltage and non-boosted voltages which are not increased from the external voltage. In the period during which a DC-DC converter section supplies a boosted voltage increased from the external voltage to an internal bias line for supplying a bias voltage to the memory cell array, a non-boosted voltage supply section for supplying a non-boosted voltage equal to or less than the external voltage is in its inactive state. In the period during which the non-boosted voltage supply section supplies a non-boosted voltage to the internal bias line, the DC-DC converter section is in its inactive state. In the period during which a boosted voltage is supplied to the internal bias line, the DC-DC converter section is used for ensuring sufficient power supply ability, and in the period during which the non-boosted voltage is supplied to the internal bias line, the DC-DC converter section can be kept in its inactive state. Thus, the power consumed by the DC-DC converter section can be saved in the period during which the supply of a boosted voltage is unnecessary.

摘要翻译： 描述了存储装置及其控制方法，根据该存储装置及其控制方法，从提供给存储单元阵列的偏置电压从从外部电压增加的升压电压和不从外部电压增加的非升压电压中选择。 在DC-DC转换器部分将从外部电压增加的升压电压提供给用于向存储单元阵列提供偏置电压的内部偏置线的期间内，提供非升压电压 等于或小于外部电压处于其无效状态。 在非升压电压供给部向内部偏置线供给非升压电压的期间，DC-DC转换部处于非活动状态。 在向内部偏置线提供升压电压的期间，DC-DC转换部用于确保充分的供电能力，在向内部偏置线供给非升压电压的期间中， DC-DC转换器部分可以保持在其非活动状态。 因此，在不需要提供升压电压的期间，可以节省DC-DC转换器部分消耗的功率。

公开(公告)号：US20060002196A1

公开(公告)日：2006-01-05

申请号：US11173735

申请日：2005-07-01

申请人： Takaaki Furuyama ,  Satoru Kawamoto

发明人： Takaaki Furuyama ,  Satoru Kawamoto

IPC分类号： G11C7/10

CPC分类号： G11C29/14 ,  G11C29/02

摘要： A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test circuit (4A) outputs write inhibit signal WINH to the memory core section (9A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (2A) and select signal S are inverted and, in response thereto, retained data DR of the data register (5A) is outputted as output data DO from the data output section (6A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.

摘要翻译： 存储器系统（1A）包括存储器部分（2A）和存储器控制部分（3A）。 存储部分（2A）包括测试电路（4A），数据寄存器（5A），数据输出部分（6A）和存储器核心部分（9A）。 数据DI保存在数据电阻（5A）中。 测试电路（4A）响应于测试信号TEST将写入禁止信号WINH输出到存储器芯部分（9A）。 识别写入指令被输入到存储部分（2A）和选择信号S的写指令识别信号WR被反转，并且作为响应，数据寄存器（5A）的保留数据DR被输出作为输出数据DO 从数据输出部分（6A）。 因此，可以测试写命令CMD和数据DI的生成，传播或识别操作是否正常，而不执行将数据写入存储器部分的存储单元的操作。

公开(公告)号：US20050157574A1

公开(公告)日：2005-07-21

申请号：US11058302

申请日：2005-02-16

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C7/00 ,  G11C11/4076 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

公开(公告)号：US06879200B2

公开(公告)日：2005-04-12

申请号：US09921561

申请日：2001-08-06

申请人： Kazufumi Komura ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Satoru Kawamoto

IPC分类号： G11C8/00 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/14 ,  H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00065

摘要： A delay circuit including a delay section having two or more predetermined delay stages is disclosed. Each predetermined delay stage adds a predetermined delay time to an input signal. The delay circuit also includes selecting switch sections. At least one of the selecting switch sections includes: a buffer section for receiving a delayed input signal from one of the delay stages and a selecting section means directly connected to the buffer section for activating the buffer section to establish a delay path, wherein an output signal from the delay path has a desired delay time.

摘要翻译： 公开了一种包括具有两个或多个预定延迟级的延迟部分的延迟电路。 每个预定延迟级向输入信号添加预定的延迟时间。 延迟电路还包括选择开关部分。 所述选择开关部分中的至少一个包括：用于从所述延迟级之一接收延迟的输入信号的缓冲器部分和直接连接到所述缓冲器部分的用于激活所述缓冲器部分以建立延迟路径的选择部分装置，其中输出 来自延迟路径的信号具有期望的延迟时间。

公开(公告)号：US06847540B2

公开(公告)日：2005-01-25

申请号：US10404153

申请日：2003-04-02

申请人： Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C11/404 ,  G11C7/14 ,  G11C7/22 ,  G11C11/34 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C7/227 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099

摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal φCPR. The signal φCPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

摘要翻译： 即使当器件状态从电源电容器的所有电荷存储节点中的没有存储电荷的状态改变到接通操作状态时，单元板电位也不波动的半导体存储器件包括NMOS晶体管M1 到Mk，用于将来自参考电压生成电路的参考电压VPR的线路VPR作为用于参考电压VCP的馈线（用于参考电压VCP的馈线）的每个单元块B1至Bk中的参考电压产生电路连接。 NMOS晶体管M1至Mk的栅极端子连接到公共信号phiCPR。 信号phiCPR在上电之后的预定时间输出正逻辑电平。 通过在每个单元块B1至Bk中设置用于使线VPR与线VCP短路的NMOS晶体管M1至Mk，在每个单元块B1至Bk中两条线都短路。