公开(公告)号：US07402485B1

公开(公告)日：2008-07-22

申请号：US11229864

申请日：2005-09-19

Applicant: William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Scott D. Luning

Inventor： William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Scott D. Luning

IPC: H01L21/8238

CPC classification number: H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

Abstract translation: 侧壁间隔结构邻近门结构形成，由此形成侧壁间隔结构的外表面的材料含有氮。 在其形成之后，侧壁间隔结构被退火以使后壁清洁过程的侧壁间隔结构硬化。 在清洁处理之后形成外延层。

公开(公告)号：US06777281B1

公开(公告)日：2004-08-17

申请号：US10214361

申请日：2002-08-08

Applicant: Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

Inventor： Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

IPC: H01L218238

CPC classification number: H01L29/6659 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823814 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semi conductor substrate including at least one dopant species-containing region extending to a surface of the substrate; (b) forming a thin liner oxide layer on the surface of the substrate; and (c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：（a）提供半导体衬底，其包括至少一个延伸到衬底表面的含掺杂物种的区域;（b）在衬底的表面上形成薄的衬里氧化物层 基材; 和（c）在细线氧化物层中并入至少一种物质，其至少一种物质，其基本上防止或至少减少其中从至少一种含掺杂物种的区域移动而引起的掺杂物质的偏析。

公开(公告)号：US06727558B1

公开(公告)日：2004-04-27

申请号：US09784790

申请日：2001-02-15

Applicant: Michael P. Duane ,  David D. Wu ,  Massud Aminpur ,  Scott D. Luning

Inventor： Michael P. Duane ,  David D. Wu ,  Massud Aminpur ,  Scott D. Luning

IPC: H01L21425

CPC classification number: H01L29/0847 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/1079 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Abstract translation: 提供了一种方法，该方法包括在衬底层上形成栅极电介质，以及在栅极电介质上方形成栅极导体。 该方法还包括在邻近栅极电介质的衬底中形成至少一个电介质隔离结构。

公开(公告)号：US06506642B1

公开(公告)日：2003-01-14

申请号：US10020931

申请日：2001-12-19

Applicant: Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

Inventor： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

IPC: H01L218238

CPC classification number: H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.

Abstract translation: 亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。 实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物， 在栅电极的已经被去除了第一侧壁间隔物的侧表面上。 实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

公开(公告)号：US06236596B1

公开(公告)日：2001-05-22

申请号：US09461376

申请日：1999-12-15

Applicant: Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

Inventor： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

IPC: G11C1134

CPC classification number: G11C16/14

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

Abstract translation: 提供了一种用于在快速EEPROM存储单元的擦除期间减小带 - 带电流的方法和装置。 该装置在衬底上具有背偏压连接，在擦除EEPROM存储单元期间施加偏置电压。 在闪存EEPROM存储单元擦除期间将偏置电压施加到反向偏置连接的方法在擦除闪速存储单元期间减少源区和衬底之间的带间电流。 这种减少提供了闪存单元的栅极尺寸减小，而不会引起有害的短沟道效应。

公开(公告)号：US6051882A

公开(公告)日：2000-04-18

申请号：US905974

申请日：1997-08-05

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Rin Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Rin Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/52

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.

Abstract translation: 一种制造导线的互连电平的方法，以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法，其使用反向镶嵌来形成导电线和通孔。 首先使用导电线图案来完全蚀刻该层以形成导电线开口。 开口完全被导电材料填充并平坦化，使得导电材料和绝缘层的表面是共面的。 通孔图案垂直于导电线对齐，并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。 由此在导电线的上部形成的开口用绝缘材料填充，以完成与绝缘层下部的导电线和层的上部向上突出的通孔的双镶嵌互连水平。 此外，通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。 所产生的互连级联结构包括具有向上和向下突出的通孔的导线。

公开(公告)号：US5888867A

公开(公告)日：1999-03-30

申请号：US23241

申请日：1998-02-13

Applicant: Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

Inventor： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

IPC: H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8247

CPC classification number: H01L29/66825 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/32155 ,  H01L29/42324 ,  H01L29/4966

Abstract: Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration. Additionally, source and drain regions are included in the substrate structure bordering the gate structure, the drain region having a differing threshold voltage than the source region.

Abstract translation: 描述了形成具有可调阈值电压的闪存EPROM单元的方面。 在方法方面，该方法包括形成衬底结构以建立细胞形成的基础，以及在衬底结构上形成具有包含不均匀Ge浓度的多晶锗（多晶硅）的浮栅的栅极结构 。 该方法还包括在衬底结构内形成源极和漏极区域，漏极区域具有与源极区域不同的阈值电压。 在另一方面，具有可调阈值电压的闪存EPROM单元包括作为单元的基础的衬底结构。 电池还包括在衬底结构上的栅极结构，栅极结构包括具有不均匀Ge浓度的多晶硅 - 锗（多晶SiGe）的浮栅。 此外，源极和漏极区域包括在与栅极结构接壤的衬底结构中，漏极区域具有与源极区域不同的阈值电压。

公开(公告)号：US5686354A

公开(公告)日：1997-11-11

申请号：US478324

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76831 ,  H01L21/76807

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.

Abstract translation: 一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。 导电线掩模图案用于在绝缘层中形成导电线路开口。 接下来，在导电线路开口中沉积有保形材料的薄保护层。 保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。 使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。 接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。 如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。 如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

公开(公告)号：US07910996B2

公开(公告)日：2011-03-22

申请号：US12496133

申请日：2009-07-01

Applicant: Paul R. Besser ,  Scott D. Luning

Inventor： Paul R. Besser ,  Scott D. Luning

IPC: H01L29/12

CPC classification number: H01L29/66628 ,  H01L29/66772

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract translation: 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US20090236664A1

公开(公告)日：2009-09-24

申请号：US12471600

申请日：2009-05-26

Applicant: David E. Brown ,  Scott D. Luning

Inventor： David E. Brown ,  Scott D. Luning

IPC: H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

Abstract: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

Abstract translation: 提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。 该方法适用于集成到集成电路半导体器件的制造工艺中。 该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。