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公开(公告)号：US20080283935A1
公开(公告)日：2008-11-20
申请号：US11750713
申请日：2007-05-18
申请人： Seetharaman Sridhar , Craig Hall
发明人： Seetharaman Sridhar , Craig Hall
IPC分类号： H01L21/336 , H01L21/76 , H01L29/06 , H01L29/94
CPC分类号： H01L21/823878 , H01L21/76232
摘要： The disclosure provides a trench isolation structure, a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device, in one embodiment, includes a substrate having a first device region and a second device region, wherein the first device region includes a first gate structure and first source/drain regions and the second device region includes a second gate structure and second source/drain regions. The semiconductor device further includes a trench isolation structure configured to isolate the first device region from the second device region, the trench isolation structure comprising: 1) an isolation trench located within the substrate, wherein the isolation trench includes an opening portion and a bulbous portion, and further wherein a maximum width of the opening portion is less than a maximum width of the bulbous portion, and 2) dielectric material substantially filling the isolation trench.
摘要翻译： 本公开提供了沟槽隔离结构，半导体器件以及半导体器件的制造方法。 在一个实施例中，半导体器件包括具有第一器件区域和第二器件区域的衬底，其中第一器件区域包括第一栅极结构和第一源极/漏极区域，并且第二器件区域包括第二栅极结构和第二栅极结构 源/漏区。 所述半导体器件还包括被配置为将所述第一器件区域与所述第二器件区域隔离的沟槽隔离结构，所述沟槽隔离结构包括：1）位于所述衬底内的隔离沟槽，其中所述隔离沟槽包括开口部分和球形部分 并且其中所述开口部分的最大宽度小于所述球形部分的最大宽度，以及2）绝缘材料基本上填充所述隔离沟槽。
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22.发明申请Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process 有权在EPI过程期间选择性地保护NMOS区域，PMOS区域和栅极层的方法公开(公告)号：US20070020839A1
公开(公告)日：2007-01-25
申请号：US11184337
申请日：2005-07-19
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.
摘要翻译： 制造具有保护衬垫和/或层的半导体器件。 阱区和隔离区形成在半导体本体内。 栅电介质层形成在半导体本体上。 在栅极电介质层上形成诸如多晶硅的栅电极层。 在栅电极层上形成保护栅衬。 形成限定栅极结构的抗蚀剂掩模。 图案化栅极电极层以形成栅极结构。 偏移间隔件形成在栅极结构的横向边缘上，然后在阱区域中形成延伸区域。 然后在门结构的侧边缘上形成侧壁间隔物。 形成覆盖器件的NMOS区域的NMOS保护区域层。 在PMOS区域内执行凹陷蚀刻，随后形成应变引发凹陷结构。
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公开(公告)号：US20060246645A1
公开(公告)日：2006-11-02
申请号：US11457569
申请日：2006-07-14
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7836 , H01L29/6659
摘要： A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of a separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current and gate-edge leakage.
摘要翻译： 描述了新的MOS晶体管。 晶体管具有包含3个部分的源极/漏极区域。 每个部分是单独的离子注入步骤的结果。 源极/漏极区域的三个部分的组合产生具有高驱动电流，低亚阈值电流和栅极边缘泄漏的优异性能的晶体管。
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公开(公告)号：US20050156236A1
公开(公告)日：2005-07-21
申请号：US10979693
申请日：2004-11-01
IPC分类号： H01L21/336 , H01L21/338 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7836 , H01L29/6659
摘要： A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of an separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current and gate-edge leakage.
摘要翻译： 描述了新的MOS晶体管。 晶体管具有包含3个部分的源极/漏极区域。 每个部分是单独的离子注入步骤的结果。 源极/漏极区域的三个部分的组合产生具有高驱动电流，低亚阈值电流和栅极边缘泄漏的优异性能的晶体管。
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公开(公告)号：US06723616B2
公开(公告)日：2004-04-20
申请号：US10253870
申请日：2002-09-24
申请人： Seetharaman Sridhar , Youngmin Kim , Zhiqiang Wu , Mark S. Rodder
发明人： Seetharaman Sridhar , Youngmin Kim , Zhiqiang Wu , Mark S. Rodder
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of forming a semiconductor device using shallow trench isolation, includes forming a trench within a semiconductor substrate and forming a screen dielectric stack outwardly from the semiconductor substrate. The screen dielectric stack includes a first sacrificial dielectric layer disposed outwardly from the semiconductor substrate and a second sacrificial dielectric layer disposed outwardly from and in contact with the first sacrificial dielectric layer. In one embodiment, the first sacrificial dielectric layer is formed before forming the trench and the second sacrificial dielectric layer is formed after forming the trench.
摘要翻译： 使用浅沟槽隔离来形成半导体器件的方法包括在半导体衬底内形成沟槽并从半导体衬底向外形成屏蔽电介质堆叠。 屏幕电介质堆叠包括从半导体衬底向外设置的第一牺牲电介质层和从第一牺牲介电层向外设置并与之接触的第二牺牲电介质层。 在一个实施例中，在形成沟槽之前形成第一牺牲电介质层，并且在形成沟槽之后形成第二牺牲绝缘层。
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26.发明授权Shallow trench isolation with conductive hard mask for in-line moat/trench width electrical measurements 有权浅沟槽隔离与导电硬掩模，用于在线护城河/沟槽宽电气测量公开(公告)号：US06204073B1
公开(公告)日：2001-03-20
申请号：US09452921
申请日：1999-12-02
IPC分类号： H01L2166
CPC分类号： H01L22/34 , H01L21/76224 , H01L22/12
摘要： A method for forming STI that allows for in-situ moat/trench width electrical measurement is disclosed herein. A conductive layer (18) is used in the hard mask (20) for trench etch. After the hard mask (20) is formed and the trench (12) is etched, the resistance of the conductive layer (18) is measured over a predefined length. Since the length is known, the average width of the hard mask (20)/moat (11) can be determined. Once the width of the moat (11) is known, the width of the trench (12) can easily be determined by subtracting the width of the moat (12) from the pitch, which is a known factor.
摘要翻译： 本文公开了一种允许原位护壕/沟槽宽度电测量的STI形成方法。 在硬掩模（20）中使用导电层（18）进行沟槽蚀刻。 在形成硬掩模（20）并且蚀刻沟槽（12）之后，在预定长度上测量导电层（18）的电阻。 由于长度是已知的，所以可以确定硬掩模（20）/护城河（11）的平均宽度。 一旦已知沟槽（11）的宽度，通过从间距减去护城河（12）的宽度可以容易地确定沟槽（12）的宽度，这是一个已知的因素。
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公开(公告)号：US08754497B2
公开(公告)日：2014-06-17
申请号：US12789040
申请日：2010-05-27
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/7846
摘要： An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.
摘要翻译： 在（100）衬底上的集成电路，其包含具有在<100>方向上取向的漂移区电流的n沟道扩展漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含n沟道延伸漏极MOS晶体管，其漂移区电流以<110>方向取向，在漂移区中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含具有沿着<110>方向取向的漂移区电流的p沟道延伸漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa拉伸应力的应力元件。
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28.发明授权Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS process flow 有权将硅锗和碳掺杂硅与应变CMOS工艺流中的源极/漏极区域集成的方法公开(公告)号：US08574979B2
公开(公告)日：2013-11-05
申请号：US12599927
申请日：2008-05-19
申请人： Seetharaman Sridhar
发明人： Seetharaman Sridhar
IPC分类号： H01L21/263 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66636
摘要： The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate (210) having a PMOS device region (220) and NMOS device region (260). Thereafter, a first gate structure (240) and a second gate structure (280) are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions (710) may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions (1110) and activated second source/drain regions (1120), respectively. Additionally, recessed epitaxial carbon doped silicon regions (1410) may be formed in the substrate on opposing sides of the second gate structure after annealing.
摘要翻译： 因此，本公开提供了一种半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括提供具有PMOS器件区域（220）和NMOS器件区域（260）的衬底（210）。 此后，分别在PMOS器件区域和NMOS器件区域上形成第一栅极结构（240）和第二栅极结构（280）。 此外，可以在第一栅极结构的相对侧上的衬底中形成凹入的外延SiGe区域（710）。 此外，第一源极/漏极区域可以形成在第二栅极结构的相对侧上，以及在第二栅极结构的相对侧上的第二源极/漏极区域。 然后可以将第一源极/漏极区域和第二源极/漏极区域退火以分别形成激活的第一源极/漏极区域（1110）和激活的第二源极/漏极区域（1120）。 此外，在退火之后，可以在第二栅极结构的相对侧上的衬底中形成凹入的外延碳掺杂硅区域（1410）。
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公开(公告)号：US08134212B2
公开(公告)日：2012-03-13
申请号：US12538594
申请日：2009-08-10
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/00 , H01L21/331 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/761 , H01L21/823493
摘要： An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC.
摘要翻译： 公开了一种在IC中包括与浅n阱结合的n型BISO层的n型隔离结构。 除了常规的n型掩埋层（NBL）之外，在p型外延层生长之前，通过将n型掺杂剂注入到p型IC衬底中来形成n型BISO层。 BISO注入层中的n型掺杂剂从p型衬底向上扩散到p型外延层的厚度的三分之一和三分之二之间。 浅的n型阱从p型外延层的顶表面延伸到n型BISO层，从p型外延层的顶表面到p型外延层形成连续的n型隔离结构 基质。 n型BISO层的宽度可以小于外延层的厚度，并且可以单独使用或与NBL一起使用以隔离IC中的元件。
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公开(公告)号：US07847351B2
公开(公告)日：2010-12-07
申请号：US12101608
申请日：2008-04-11
IPC分类号： H01L29/76
CPC分类号： H01L29/402 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.
摘要翻译： 一种包括源极和漏极区域以及绝缘区域和板状结构的半导体器件。 源区和漏区在半导体衬底上或半导体衬底中。 绝缘区域位于或位于半导体衬底中并位于源区和漏区之间。 绝缘区域具有薄层和厚层。 厚层包括彼此分离并且跨越源极和漏极区域之间的长度延伸的多个绝缘条。 板结构位于源区和漏区之间，其中板结构位于薄层和厚层的部分上，板结构具有一个或多个导电带，其直接位于多个绝缘中的单独绝缘层上 条纹。
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