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    Process of increasing screen dielectric thickness
    1.
    发明授权
    Process of increasing screen dielectric thickness 有权
    屏幕介电厚度增加的过程

    公开(公告)号：US06723616B2

    公开(公告)日：2004-04-20

    申请号：US10253870

    申请日：2002-09-24

    申请人： Seetharaman Sridhar ,  Youngmin Kim ,  Zhiqiang Wu ,  Mark S. Rodder

    发明人： Seetharaman Sridhar ,  Youngmin Kim ,  Zhiqiang Wu ,  Mark S. Rodder

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232

    摘要： A method of forming a semiconductor device using shallow trench isolation, includes forming a trench within a semiconductor substrate and forming a screen dielectric stack outwardly from the semiconductor substrate. The screen dielectric stack includes a first sacrificial dielectric layer disposed outwardly from the semiconductor substrate and a second sacrificial dielectric layer disposed outwardly from and in contact with the first sacrificial dielectric layer. In one embodiment, the first sacrificial dielectric layer is formed before forming the trench and the second sacrificial dielectric layer is formed after forming the trench.

    摘要翻译： 使用浅沟槽隔离来形成半导体器件的方法包括在半导体衬底内形成沟槽并从半导体衬底向外形成屏蔽电介质堆叠。 屏幕电介质堆叠包括从半导体衬底向外设置的第一牺牲电介质层和从第一牺牲介电层向外设置并与之接触的第二牺牲电介质层。 在一个实施例中，在形成沟槽之前形成第一牺牲电介质层，并且在形成沟槽之后形成第二牺牲绝缘层。

    High performance PNP bipolar device fully compatible with CMOS process
    2.
    发明授权
    High performance PNP bipolar device fully compatible with CMOS process 有权
    高性能PNP双极器件完全兼容CMOS工艺

    公开(公告)号：US06794730B2

    公开(公告)日：2004-09-21

    申请号：US10028002

    申请日：2001-12-20

    申请人： Youngmin Kim ,  Shaoping Tang ,  Seetharaman Sridhar ,  Amitava Chatterjee

    发明人： Youngmin Kim ,  Shaoping Tang ,  Seetharaman Sridhar ,  Amitava Chatterjee

    IPC分类号： H01L27082

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804

    摘要： A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

    摘要翻译： 通过减小p阱注入的深度以增加发射极中的载流子浓度并使发射极结更深以增加发射极中的少数寿命，形成pnp双极结型晶体管，其具有改善的发射极效率。 形成高增益BJT，而不对工艺流程添加掩模步骤。 在优选实施例中，使用覆盖的高能量硼注入来抑制SRAM中的隔离泄漏。

    Thick gate oxide for LDMOS and DEMOS
    3.
    发明授权
    Thick gate oxide for LDMOS and DEMOS 有权
    LDMOS和DEMOS的厚栅氧化物

    公开(公告)号：US08470675B2

    公开(公告)日：2013-06-25

    申请号：US13274698

    申请日：2011-10-17

    申请人： Seetharaman Sridhar ,  Sameer Pendharkar

    发明人： Seetharaman Sridhar ,  Sameer Pendharkar

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823456 ,  H01L21/823462

    摘要： A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.

    摘要翻译： 一种形成集成电路的工艺，包括形成用于离子注入低电压晶体管的虚拟氧化物层，用较薄的栅极电介质层代替低电压晶体管区域中的虚拟氧化物，并将用于DEMOS的栅极电介质的虚拟氧化物 或LDMOS晶体管。 一种形成集成电路的工艺，包括形成用于离子注入低压和中压晶体管的虚拟氧化物层，用较薄的栅介质层代替低电压晶体管中的虚拟氧化物，用中间电压晶体管替代中间电压晶体管中的虚拟氧化物， 另一栅极电介质层，并且保留用于DEMOS或LDMOS晶体管的栅极电介质的虚拟氧化物。

    Lateral metal oxide semiconductor drain extension design
    4.
    发明授权
    Lateral metal oxide semiconductor drain extension design 有权
    横向金属氧化物半导体漏极扩展设计

    公开(公告)号：US08426281B2

    公开(公告)日：2013-04-23

    申请号：US12961885

    申请日：2010-12-07

    申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

    发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.

    摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹

    Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom
    5.
    发明授权
    Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom 有权
    包括具有多个栅介质厚度的工艺和其集成电路的沟槽隔离

    公开(公告)号：US07888196B2

    公开(公告)日：2011-02-15

    申请号：US12345072

    申请日：2008-12-29

    申请人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

    发明人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823462 ,  H01L21/76229 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878

    摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness

    摘要翻译： 一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管， 其中所述第一厚度<所述第二厚度。 提供具有半导体表面的衬底。 具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。 在包括第二区域的半导体表面上形成硬掩模层。 通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。 多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。 在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。 然后完成第一和第二区域中的MOS晶体管的制造。

    METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW
    6.
    发明申请
    METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW 审中-公开
    在应变CMOS流中积聚硅锗和碳掺杂硅的方法

    公开(公告)号：US20080283926A1

    公开(公告)日：2008-11-20

    申请号：US11750690

    申请日：2007-05-18

    申请人： Seetharaman Sridhar

    发明人： Seetharaman Sridhar

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/66636 ,  H01L29/7848

    摘要： The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate having a PMOS device region and NMOS device region. Thereafter, a first gate structure and a second gate structure are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions and activated second source/drain regions, respectively. Additionally, recessed epitaxial carbon doped silicon regions may be formed in the substrate on opposing sides of the second gate structure after annealing.

    摘要翻译： 因此，本公开提供了一种半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括提供具有PMOS器件区和NMOS器件区的衬底。 此后，分别在PMOS器件区域和NMOS器件区域上形成第一栅极结构和第二栅极结构。 此外，可以在第一栅极结构的相对侧上的衬底中形成凹入的外延SiGe区域。 此外，第一源极/漏极区域可以形成在第二栅极结构的相对侧上，以及在第二栅极结构的相对侧上的第二源极/漏极区域。 然后可以将第一源极/漏极区域和第二源极/漏极区域退火以分别形成激活的第一源极/漏极区域和激活的第二源极/漏极区域。 此外，在退火之后，可以在第二栅极结构的相对侧上的衬底中形成凹入的外延碳掺杂硅区。

    Application of different isolation schemes for logic and embedded memory
    7.
    发明授权
    Application of different isolation schemes for logic and embedded memory 有权
    不同隔离方案在逻辑和嵌入式存储器中的应用

    公开(公告)号：US07314800B2

    公开(公告)日：2008-01-01

    申请号：US11296164

    申请日：2005-12-07

    申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

    发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

    IPC分类号： H01L21/00

    CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

    摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

    摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

    Method to selectively recess ETCH regions on a wafer surface using capoly as a mask
    8.
    发明授权
    Method to selectively recess ETCH regions on a wafer surface using capoly as a mask 有权
    使用capoly作为掩模来选择性地在晶片表面上凹入ETCH区域的方法

    公开(公告)号：US07169659B2

    公开(公告)日：2007-01-30

    申请号：US10931195

    申请日：2004-08-31

    申请人： Antonio L. P. Rotondaro ,  Seetharaman Sridhar

    发明人： Antonio L. P. Rotondaro ,  Seetharaman Sridhar

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).

    摘要翻译： 本发明通过提供制造方法来促进半导体制造，该方法选择性地将应变应用于器件的沟道区，同时减轻所采用的掩模操作。 在半导体器件（102）的NMOS区域上形成CAPOLY层。 在半导体器件（104）的PMOS区域内的器件的有源区域上执行凹蚀刻，并且CAPOLY层防止在半导体器件的NMOS区域内的器件的蚀刻。 随后，执行形成或沉积外延区域并在PMOS区域中的沟道区域上引入第一类型的应变的外延形成工艺（106）。 然后，半导体器件被退火（108）以使CAPOLY层在NMOS区域中的沟道区域上引入第二类型的应变。 退火后，去除CAPOLY层（110）。

    Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions
    10.
    发明授权
    Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions 有权
    在形成晶体管的漏极延伸和凹陷的应变外延区域期间使用单个掩模

    公开(公告)号：US07892931B2

    公开(公告)日：2011-02-22

    申请号：US11613798

    申请日：2006-12-20

    申请人： Seetharaman Sridhar ,  Majid Mansoori

    发明人： Seetharaman Sridhar ,  Majid Mansoori

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method 300 for forming a transistor's drain extension 70 and recessed strained epi regions 150 with a single mask step 306. In an example embodiment, the method 300 may include forming a patterned photoresist layer 200 over a protection layer 190 in a NMOS region 50 and then etching exposed portions of the protection layer 190 in the PMOS region 60 to form extension sidewalls 210 on the transistors 30 in the PMOS region 60 plus a protective hardmask 220 over the NMOS region 50. The method 300 may further include forming the extension regions 70 for the PMOS region transistors 30, performing a recess etch 240 of active regions 230 of the PMOS region transistors 30, and forming the recessed strained epi regions 150.

    摘要翻译： 用于用单个掩模步骤306形成晶体管漏极延伸70和凹陷的应变外延区域150的方法300.在示例实施例中，方法300可以包括在NMOS区域50中的保护层190上形成图案化的光致抗蚀剂层200， 然后蚀刻PMOS区域60中的保护层190的暴露部分，以在PMOS区域60中的晶体管30上加上NMOS区域50上的保护性硬掩模220形成延伸侧壁210.方法300还可以包括形成延伸区域70 对于PMOS区域晶体管30，执行PMOS区晶体管30的有源区230的凹陷蚀刻240，并形成凹陷的应变外延区域150。