公开(公告)号：US20110256715A1

公开(公告)日：2011-10-20

申请号：US12761805

申请日：2010-04-16

Applicant: Shing-Chyang PAN ,  Han-Hsin KUO ,  Chung-Chi KO ,  Ching-Hua HSIEH

Inventor： Shing-Chyang PAN ,  Han-Hsin KUO ,  Chung-Chi KO ,  Ching-Hua HSIEH

IPC: H01L21/768 ,  C23C14/06 ,  B05D7/22

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76861 ,  H01L21/76867 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide.

Abstract translation: 铜互连包括在电介质层中形成的铜层。 在铜层和电介质层之间形成衬垫。 在衬垫和电介质层之间的边界处形成阻挡层。 阻挡层是金属氧化物。

公开(公告)号：US07805258B2

公开(公告)日：2010-09-28

申请号：US11707662

申请日：2007-02-16

Applicant: Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

Inventor： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

IPC: G06F19/00 ,  G06F17/40

CPC classification number: G01R31/2831 ,  H01L22/12

Abstract: A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.

Abstract translation: 在晶片上形成当前顶层之后测试晶片的方法。 在形成当前顶层之后，为晶片收集应力数据。 应力数据来源于晶片曲率的变化。 应力数据包括：在x方向上的应力x x和在晶片上的一组有限区域的每个区域的ay方向上的应力yy，应力xx和应力yy都源自晶片曲率变化 - x x在x方向上对于有限区域集合中的每个区域以及从y方向的晶片曲率变化yy到该有限区域集合中的每个区域; 并且应力xy从晶片曲率变化xy得到，其中晶片曲率变化xy是在该有限区域的每个区域的x-y平面中的晶片扭转的变化。 应力梯度矢量（和/或其范数）被计算并用于评估调查单个或多个累积层。

公开(公告)号：US07704886B2

公开(公告)日：2010-04-27

申请号：US12031280

申请日：2008-02-14

Applicant: Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.

Abstract translation: 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行第一沉积步骤以在第一室中形成种子层; 以及执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括执行第二沉积步骤以增加种子层的厚度。 在与第一室不同的第二室中执行第一蚀刻步骤和第二沉积步骤中的至少一个。

公开(公告)号：US20090209106A1

公开(公告)日：2009-08-20

申请号：US12031108

申请日：2008-02-14

Applicant: Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

Inventor： Li-Lin Su ,  Cheng-Lin Huang ,  Shing-Chyang Pan ,  Ching-Hua Hsieh

IPC: H01L21/311

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.

Abstract translation: 形成互连结构的籽晶层的方法包括形成介电层; 在介电层中形成开口; 执行第一沉积步骤以形成种子层; 并且原位执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括用于形成种子层的附加沉积和蚀刻步骤。

公开(公告)号：US07453149B2

公开(公告)日：2008-11-18

申请号：US11024916

申请日：2004-12-28

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC: H01L23/48

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

Abstract translation: 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

公开(公告)号：US07253501B2

公开(公告)日：2007-08-07

申请号：US10909980

申请日：2004-08-03

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Cheng-Lin Huang ,  Li-Lin Su ,  Shau-Lin Shue

IPC: H01L23/58 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract translation: 一种具有包括第一金属元件的非导电盖层的半导体器件。 非导电盖层包括导电线上的第一金属氮化物，第一金属氧化物或第一金属氧氮化物，以及导电线之间的绝缘材料。 界面区域可以形成在导电线的顶表面上，界面区域包括盖层的金属元件。 盖层防止导电线中的导电材料迁移或扩散到相邻的随后形成的绝缘材料层中。 盖层也可以用作蚀刻停止层。

公开(公告)号：US07247252B2

公开(公告)日：2007-07-24

申请号：US10175613

申请日：2002-06-20

Applicant: Shing-Chyang Pan ,  Yu-Chun Huang ,  Shwangming Jing

Inventor： Shing-Chyang Pan ,  Yu-Chun Huang ,  Shwangming Jing

IPC: H01L21/30

CPC classification number: H01L21/31138 ,  H01L21/31116

Abstract: A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process; treating the deposition layer portion with a hydrogen plasma treatment to reduce an electrical charge nonuniformity of the deposition layer including applying a biasing power to the semiconductor wafer; and, carrying out a subsequent reactive ion etching process.

Abstract translation: 一种用于在反应离子蚀刻（RIE）过程中避免等离子体电弧的方法，包括提供具有用于沉积介电绝缘层的工艺表面的半导体晶片; 沉积介电绝缘层的至少一部分以根据等离子体辅助化学气相沉积（CVD）工艺形成沉积层; 用氢等离子体处理处理沉积层部分以减少沉积层的电荷不均匀性，包括向半导体晶片施加偏压功率; 并进行后续的反应离子蚀刻工艺。

公开(公告)号：US07193327B2

公开(公告)日：2007-03-20

申请号：US11042396

申请日：2005-01-25

Applicant: Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

Abstract translation: 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

公开(公告)号：US20060163746A1

公开(公告)日：2006-07-27

申请号：US11042396

申请日：2005-01-25

Applicant: Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

Abstract translation: 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

公开(公告)号：US20060027925A1

公开(公告)日：2006-02-09

申请号：US11024916

申请日：2004-12-28

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC: H01L29/788

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

Abstract translation: 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。