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    Layout pattern of magnetoresistive random access memory
    23.
    发明授权
    Layout pattern of magnetoresistive random access memory 有权

    公开(公告)号：US12190926B2

    公开(公告)日：2025-01-07

    申请号：US18108025

    申请日：2023-02-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

    IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

    Manufacturing method of semiconductor device
    26.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US12183809B2

    公开(公告)日：2024-12-31

    申请号：US17673819

    申请日：2022-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

    SEMICONDUCTOR DEVICE
    28.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240429316A1

    公开(公告)日：2024-12-26

    申请号：US18822485

    申请日：2024-09-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Jhe Hsu ,  Che-Yi Ho

    IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165

    Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.

    Current generator with reduced power consumption
    30.
    发明授权
    Current generator with reduced power consumption 有权

    公开(公告)号：US12176800B2

    公开(公告)日：2024-12-24

    申请号：US18081706

    申请日：2022-12-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiu-Ming Yeh ,  Min-Chia Wang

    IPC: H02M1/00 ,  H02M3/155

    Abstract: A current generator includes a startup circuit and a bandgap reference circuit coupled to the startup circuit. The startup circuit is for generating a first voltage. The bandgap reference circuit is for generating a second voltage. The bandgap reference circuit includes an operational amplifier. The operational amplifier includes a bias source circuit and a bias generator circuit. The bias source circuit is for generating a reference current according to the first voltage and the second voltage. The bias generator circuit is for generating bias voltages according to the reference current. The startup circuit and the bandgap reference circuit receive a supply voltage.

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