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    Method of manufacturing copper interconnect
    23.
    发明授权
    Method of manufacturing copper interconnect 有权
    制造铜互连的方法

    公开(公告)号：US06265313B1

    公开(公告)日：2001-07-24

    申请号：US09191632

    申请日：1998-11-13

    Applicant: Yimin Huang ,  Tri-Rung Yew ,  Water Lur

    Inventor： Yimin Huang ,  Tri-Rung Yew ,  Water Lur

    IPC: H01L2144

    CPC classification number: H01L21/76865 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76844 ,  H01L21/76862 ,  Y10S438/906

    Abstract: A method of manufacturing copper interconnects includes the steps of first providing a semiconductor substrate having a dielectric layer thereon. The dielectric layer further includes a copper layer embedded within. An inter-metal dielectric layer is deposited over the dielectric layer. A via opening and a trench opening that exposes a portion of the copper layer are formed in the inter-metal dielectric layer. A thin barrier layer is formed over the exposed copper layer at the bottom of the via opening. The bottom part of the via opening is bombarded by atoms until the copper layer is exposed. Copper material is deposited to fill the via opening and the trench opening, thereby forming a damascene structure.

    Abstract translation: 制造铜互连的方法包括以下步骤：首先在其上提供具有介电层的半导体衬底。 电介质层还包括嵌入其中的铜层。 在介电层上沉积金属间介电层。 在金属间介电层中形成通孔开口和暴露一部分铜层的沟槽开口。 在通孔开口的底部的暴露的铜层上形成薄的阻挡层。 通孔开口的底部被原子轰击直到铜层暴露。 沉积铜材料以填充通孔开口和沟槽开口，从而形成镶嵌结构。

    Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern
    24.
    发明授权
    Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern 失效
    通过形成浅虚拟图案提高化学机械抛光操作的表面平面度的方法

    公开(公告)号：US06214745B1

    公开(公告)日：2001-04-10

    申请号：US09195685

    申请日：1998-11-19

    Applicant: Ming-Sheng Yang ,  Yimin Huang ,  Juan-Yuan Wu ,  Water Lur

    Inventor： Ming-Sheng Yang ,  Yimin Huang ,  Juan-Yuan Wu ,  Water Lur

    IPC: H01L2131

    CPC classification number: H01L21/7684 ,  H01L21/3212

    Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.

    Abstract translation: 化学机械抛光方法利用浅哑图形来平坦化介电层。 该方法包括以下步骤：首先在电介质层上形成浅哑图案，然后在电介质层上涂覆图案化的光致抗蚀剂层。 此后，将光致抗蚀剂层用作掩模以在电介质层的其它区域中形成开口。 随后，去除光致抗蚀剂层以露出浅哑图案，然后依次沉积胶/阻挡层和导电层。 接下来，进行化学机械抛光操作，以同时去除介电层上方的多余的导电层和胶/阻挡层以及浅哑图案。 由于介电层上方的每个区域中胶/阻挡层的去除速率大致相同，所以获得了平坦的基板表面。

    Method of forming dual damascene structure
    25.
    发明授权
    Method of forming dual damascene structure 失效

    公开(公告)号：US6060379A

    公开(公告)日：2000-05-09

    申请号：US123342

    申请日：1998-07-28

    Applicant: Yimin Huang ,  Tri-Rung Yew

    Inventor： Yimin Huang ,  Tri-Rung Yew

    IPC: H01L21/768 ,  H01L21/4763

    CPC classification number: H01L21/76829 ,  H01L21/76807

    Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

    Method of manufacturing multilevel metal interconnect
    26.
    发明授权
    Method of manufacturing multilevel metal interconnect 有权
    制造多层金属互连的方法

    公开(公告)号：US6048796A

    公开(公告)日：2000-04-11

    申请号：US211891

    申请日：1998-12-15

    Applicant: Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang ,  Chih-Chien Liu ,  Water Lur

    Inventor： Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang ,  Chih-Chien Liu ,  Water Lur

    IPC: H01L21/768 ,  H01L21/00

    CPC classification number: H01L21/7684 ,  H01L21/76829

    Abstract: A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.

    Abstract translation: 描述了一种用于制造多层金属互连的方法。 该方法包括以下步骤：提供衬底，然后在衬底上形成线。 在基板和导线上形成电介质层，在电介质层上形成保护层。 通过图案化保护层和电介质层形成开口，并且在保护层和开口中形成阻挡层。 在阻挡层上形成铜层并填充开口。 通过化学机械抛光去除铜层和阻挡层的一部分。

    Dual damascene processing method
    27.
    发明授权
    Dual damascene processing method 失效
    双镶嵌加工方法

    公开(公告)号：US6001414A

    公开(公告)日：1999-12-14

    申请号：US991193

    申请日：1997-12-16

    Applicant: Yimin Huang ,  Hsiao-Pang Chou ,  Tri-Rung Yew

    Inventor： Yimin Huang ,  Hsiao-Pang Chou ,  Tri-Rung Yew

    IPC: H01L21/768 ,  B05D5/12

    CPC classification number: H01L21/76829 ,  H01L21/76804

    Abstract: A dual damascene processing method comprising the steps depositing sequentially a first oxide layer, a SRO layer and a second oxide layer over a substrate. Then, photolithographic and etching operations are conducted to form a via that links up with a desired wire-connecting region above the substrate. Next, another photolithographic and etching operations are conducted to form interconnect trench lines followed by the deposition of metal into the via and trench. Finally, the surface is polished with a chemical-mechanical polishing operation to remove the unwanted metal on the surface. The invention is capable of controlling the depth of trench and obtaining a smoother trench bottom for the metal lines. Furthermore, the separation of via and trench etching steps makes the control of the final etch profile much easier, thereby able to get an optimal result.

    Abstract translation: 一种双镶嵌加工方法，包括以下步骤：在基材上依次沉积第一氧化物层，SRO层和第二氧化物层。 然后，进行光刻和蚀刻操作以形成与基板上方的期望的线连接区域连接的通孔。 接下来，进行另一光刻和蚀刻操作以形成互连沟槽线，随后将金属沉积到通孔和沟槽中。 最后，通过化学机械抛光操作抛光表面以除去表面上不需要的金属。 本发明能够控制沟槽的深度并为金属线获得更​​平滑的沟槽底部。 此外，通孔和沟槽蚀刻步骤的分离使得最终蚀刻轮廓的控制更容易，从而能够获得最佳结果。

    Dual damascence process
    28.
    发明授权
    Dual damascence process 失效
    双重大马士革过程

    公开(公告)号：US5990015A

    公开(公告)日：1999-11-23

    申请号：US41567

    申请日：1998-03-12

    Applicant: Tony Lin ,  Yimin Huang ,  Tri-Rung Yew

    Inventor： Tony Lin ,  Yimin Huang ,  Tri-Rung Yew

    IPC: H01L21/768 ,  H01L21/44

    CPC classification number: H01L21/76813 ,  H01L21/76807

    Abstract: A dual damascene process can be used to form an interconnect. A first dielectric layer is formed on a semiconductor substrate having a device layer formed thereon. A stop layer is formed on the first dielectric layer and a second dielectric layer is formed on the stop layer. A hard mask layer is formed and patterned on the second dielectric layer so that an opening is formed to expose the second dielectric layer therewithin. The second dielectric layer, the stop layer and a part of the first dielectric layer are etched within the opening by photolithography and etching, so that a contact window is formed. Using the hard mask layer as a hard mask, an etching is performed so that a metal trench penetrating through the second dielectric layer is formed, and the device layer within the contact window is exposed.

    Abstract translation: 可以使用双镶嵌工艺来形成互连。 在其上形成有器件层的半导体衬底上形成第一介电层。 在第一电介质层上形成阻挡层，在停止层上形成第二电介质层。 在第二电介质层上形成并图案化硬掩模层，从而形成开口以在其中露出第二介电层。 通过光刻和蚀刻在开口内蚀刻第二介电层，停止层和第一介电层的一部分，从而形成接触窗。 使用硬掩模层作为硬掩模，进行蚀刻，从而形成穿过第二介电层的金属沟槽，并且暴露接触窗内的器件层。

    POLY RESISTOR DESIGN FOR REPLACEMENT GATE TECHNOLOGY
    30.
    发明申请
    POLY RESISTOR DESIGN FOR REPLACEMENT GATE TECHNOLOGY 审中-公开
    用于替代盖茨技术的聚电阻设计

    公开(公告)号：US20130228878A1

    公开(公告)日：2013-09-05

    申请号：US13411127

    申请日：2012-03-02

    Applicant: Pai-Chieh WANG ,  Yimin HUANG

    Inventor： Pai-Chieh WANG ,  Yimin HUANG

    IPC: H01L29/78 ,  H01L21/76

    CPC classification number: H01L21/76224 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A semiconductor device and method for fabricating a semiconductor device are disclosed. The semiconductor device comprises a semiconductor substrate; an active region of the substrate, wherein the active region includes at least one transistor; and a passive region of the substrate, wherein the passive region includes at least one resistive structure disposed on an isolation region, the at least one resistive structure in a lower plane than the at least one transistor

    Abstract translation: 公开了一种用于制造半导体器件的半导体器件和方法。 半导体器件包括半导体衬底; 所述衬底的有源区，其中所述有源区包括至少一个晶体管; 和所述衬底的无源区域，其中所述无源区域包括设置在隔离区域上的至少一个电阻结构，所述至少一个电阻结构在比所述至少一个晶体管的下平面

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