Method of manufacturing multilevel metal interconnect
    1.
    发明授权
    Method of manufacturing multilevel metal interconnect 有权
    制造多层金属互连的方法

    公开(公告)号:US6048796A

    公开(公告)日:2000-04-11

    申请号:US211891

    申请日:1998-12-15

    IPC分类号: H01L21/768 H01L21/00

    CPC分类号: H01L21/7684 H01L21/76829

    摘要: A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.

    摘要翻译: 描述了一种用于制造多层金属互连的方法。 该方法包括以下步骤:提供衬底,然后在衬底上形成线。 在基板和导线上形成电介质层,在电介质层上形成保护层。 通过图案化保护层和电介质层形成开口,并且在保护层和开口中形成阻挡层。 在阻挡层上形成铜层并填充开口。 通过化学机械抛光去除铜层和阻挡层的一部分。

    Method of fabricating a copper capping layer
    2.
    发明授权
    Method of fabricating a copper capping layer 有权
    铜覆盖层的制造方法

    公开(公告)号:US06339025B1

    公开(公告)日:2002-01-15

    申请号:US09304436

    申请日:1999-04-03

    IPC分类号: H01L2144

    摘要: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

    摘要翻译: 一种制造铜覆盖层的方法。 在暴露的铜层上形成富氮的氮化物层。 由于富含硅的氮化物层内部具有更多的悬空键,富硅氮化物层中的硅容易与铜反应,并且在铜和富硅氮化物层之间形成铜硅化物层。 因此,可以提高铜和富硅氮化物层的粘合性。

    Method for forming an inter-metal dielectric layer
    3.
    发明授权
    Method for forming an inter-metal dielectric layer 有权
    形成金属间介电层的方法

    公开(公告)号:US06218284B1

    公开(公告)日:2001-04-17

    申请号:US09241841

    申请日:1999-02-01

    IPC分类号: H01L2176

    摘要: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

    摘要翻译: 描述了一种在没有空隙的情况下形成金属间介电层的方法。 在所提供的基板上形成接线。 每条布线包括其上的保护层。 在衬底上方和衬底上形成衬里层。 通过使用高密度等离子体化学气相沉积(HDPCVD)在衬层上形成氟化硅酸盐玻璃(FSG)层。 FSG层的厚度约为布线厚度的0.9-1倍。 使用HDPCVD在FSG层上形成覆盖层。 盖层的厚度为布线的厚度的约0.2-0.3倍。 在盖层上形成氧化层以达到预定的厚度。 去除介电层的一部分以获得平坦化表面。

    Method of forming an undoped silicate glass layer on a semiconductor
wafer
    4.
    发明授权
    Method of forming an undoped silicate glass layer on a semiconductor wafer 有权
    在半导体晶片上形成未掺杂的硅酸盐玻璃层的方法

    公开(公告)号:US6001746A

    公开(公告)日:1999-12-14

    申请号:US314928

    申请日:1999-05-20

    IPC分类号: C23C16/40 H01L21/316

    摘要: The present invention provides a method of forming an undoped silicate glass layer on a semiconductor wafer by performing a high density plasma chemical vapor deposition process. The semiconductor wafer being positioned in a deposition chamber. The method comprises forming the undoped silicate glass layer by performing the high density plasma chemical vapor deposition process in the deposition chamber under the following conditions: an argon (Ar) flow rate of 40 to 70 sccm (standard cubic centimeter per minute); an oxygen (O.sub.2) flow rate of 90 to 120 sccm; a silane flow rate of 70 to 100 sccm; a gas pressure of 3 to 10 mtorr; a temperature of 300 to 400.degree. C.; and a low frequency power of 2500 to 3500 watts. Wherein the ratio of Ar to O.sub.2 is 0.53, and O.sub.2 to silane is 1.23.

    摘要翻译: 本发明提供了通过进行高密度等离子体化学气相沉积工艺在半导体晶片上形成未掺杂的硅酸盐玻璃层的方法。 半导体晶片位于沉积室中。 该方法包括通过在以下条件下在沉积室中进行高密度等离子体化学气相沉积工艺来形成未掺杂的硅酸盐玻璃层:氩(Ar)流速为40至70sccm(标准立方厘米每分钟); 氧气(O 2)流量为90至120sccm; 硅烷流量为70〜100sccm; 气体压力为3至10毫托; 温度为300〜400℃。 和2500至3500瓦的低频功率。 其中Ar与O 2的比例为0.53,O 2与硅烷的比例为1.23。