公开(公告)号：US06500496B1

公开(公告)日：2002-12-31

申请号：US09695959

申请日：2000-10-25

Applicant: Matthew J. Goeckner ,  Ziwei Fang

Inventor： Matthew J. Goeckner ,  Ziwei Fang

IPC: C23C1400

CPC classification number: H01J37/32596 ,  C23C14/48 ,  H01J37/34 ,  H01J37/3438

Abstract: A plasma doping apparatus includes a hollow cathode to increase throughput and uniformity of ion implantations in a target. The hollow cathode is located adjacent an anode and a target cathode on which a target is placed. An ionizable gas is provided in a space between the anode and the target cathode. The space in which the ionizable gas is provided is surrounded by the hollow cathode. The hollow cathode has either a circular or rectangular cross-section.

Abstract translation: 等离子体掺杂装置包括空心阴极以增加目标中的离子注入的产量和均匀性。 中空阴极位于邻近阳极和放置目标物体的目标阴极。 在阳极和目标阴极之间的空间中提供可电离气体。 可提供可离子化气体的空间被中空阴极包围。 中空阴极具有圆形或矩形横截面。

公开(公告)号：US20130017660A1

公开(公告)日：2013-01-17

申请号：US13183043

申请日：2011-07-14

Applicant: Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

Inventor： Ziwei Fang ,  Ying Zhang ,  Jeff J. Xu

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/30617 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 在一个示例中，该方法包括在衬底上形成栅极结构; 在衬底中形成掺杂区域; 执行第一蚀刻工艺以去除掺杂区域并在衬底中形成沟槽; 以及执行通过去除衬底的部分来修改沟槽的第二蚀刻工艺。

公开(公告)号：US20120190167A1

公开(公告)日：2012-07-26

申请号：US13156939

申请日：2011-06-09

Applicant: Yu-Lien HUANG ,  Chun Hsiung TSAI ,  Chii-Ming WU ,  Ziwei FANG

Inventor： Yu-Lien HUANG ,  Chun Hsiung TSAI ,  Chii-Ming WU ,  Ziwei FANG

IPC: H01L21/762 ,  B82Y40/00

CPC classification number: H01L21/76229

Abstract: The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

Abstract translation: 所描述的实施例提供了用碳掺杂STI中的氧化物的机制，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。 这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。 硬掩模层可用于保护下面的硅不被掺杂。 通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

公开(公告)号：US20120187524A1

公开(公告)日：2012-07-26

申请号：US13012948

申请日：2011-01-25

Applicant: Yu-Lien HUANG ,  Chun Hsiung TSAI ,  Chii-Ming WU ,  Ziwei FANG

Inventor： Yu-Lien HUANG ,  Chun Hsiung TSAI ,  Chii-Ming WU ,  Ziwei FANG

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L21/76237 ,  H01L21/02321 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224

Abstract: The embodiments described provide methods and structures for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

Abstract translation: 所描述的实施例提供了用碳掺杂STI中的氧化物的方法和结构，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。 这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。 硬掩模层可用于保护下面的硅不被掺杂。 通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

公开(公告)号：US20090283670A1

公开(公告)日：2009-11-19

申请号：US12272537

申请日：2008-11-18

Applicant: Bon-Woong Koo ,  Ludovic Godet ,  Vassilis Panayotis Vourloumis ,  Vikram Singh ,  Ziwei Fang

Inventor： Bon-Woong Koo ,  Ludovic Godet ,  Vassilis Panayotis Vourloumis ,  Vikram Singh ,  Ziwei Fang

IPC: B01D59/44 ,  H01J49/00

CPC classification number: H01J37/32422 ,  H01J37/32935

Abstract: A time-of-flight ion sensor for monitoring ion species in a plasma includes a housing. A drift tube is positioned in the housing. An extractor electrode is positioned in the housing at a first end of the drift tube so as to attract ions from the plasma. A plurality of electrodes is positioned at a first end of the drift tube proximate to the extractor electrode. The plurality of electrodes is biased so as to selectively attract ions to enter the drift tube and to drift towards a second end of the drift tube. An ion detector is positioned proximate to the second end of the drift tube. The ion detector detects arrival times associated with the at least the portion of the attracted ions.

Abstract translation: 用于监测等离子体中的离子种类的飞行时间离子传感器包括壳体。 漂移管位于外壳中。 提取器电极位于漂移管的第一端处的壳体中，以便从等离子体吸引离子。 多个电极位于漂移管的靠近提取器电极的第一端。 多个电极被偏置以选择性地吸引离子进入漂移管并漂移到漂移管的第二端。 离子检测器位于漂移管的第二端附近。 离子检测器检测与吸引的离子的至少一部分相关联的到达时间。

公开(公告)号：US20090104761A1

公开(公告)日：2009-04-23

申请号：US11875062

申请日：2007-10-19

Applicant: Yongbae Jeon ,  Vikram Singh ,  Timothy Miller ,  Ziwei Fang ,  Steven Walther ,  Atul Gupta

Inventor： Yongbae Jeon ,  Vikram Singh ,  Timothy Miller ,  Ziwei Fang ,  Steven Walther ,  Atul Gupta

IPC: H01L21/26 ,  C23C16/513

CPC classification number: H01J37/32642 ,  H01J37/32412 ,  H01J37/32935

Abstract: A method of plasma doping includes generating a plasma comprising dopant ions proximate to a platen supporting a substrate in a plasma chamber. The platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. At least one sensor measuring data related to charging conditions favorable for forming an electrical discharge is monitored. At least one plasma process parameter is modified in response to the measured data, thereby reducing a probability of forming an electrical discharge.

Abstract translation: 等离子体掺杂的方法包括产生等离子体，该等离子体包括邻近于在等离子体室中支撑衬底的压板的掺杂剂离子。 压板被具有负电位的偏压电压波形偏置，其将等离子体中的离子吸引到用于等离子体掺杂的衬底。 监测至少一个测量与有利于形成放电的充电条件有关的数据的传感器。 响应于测量数据修改至少一个等离子体处理参数，从而降低形成放电的可能性。

公开(公告)号：US06528805B2

公开(公告)日：2003-03-04

申请号：US09916998

申请日：2001-07-27

Applicant: Ziwei Fang ,  Matthew Goeckner

Inventor： Ziwei Fang ,  Matthew Goeckner

IPC: H01J37244

CPC classification number: H01J37/32412 ,  H01J37/32935 ,  H01J2237/24405 ,  H01J2237/31703

Abstract: Plasma doping apparatus includes a plasma doping chamber, a platen mounted in the plasma doping chamber for supporting a workpiece such as a semiconductor wafer, a source of ionizable gas coupled to the chamber, an anode spaced from the platen and a pulse source for applying voltage pulses between the platen and the anode. The voltage pulses produce a plasma having a plasma sheath in the vicinity of the workpiece. The voltage pulses accelerate positive ions across the plasma sheath toward the platen for implantation into the workpiece. The plasma doping apparatus includes at least one Faraday cup positioned adjacent to the platen for collecting a sample of the positive ions accelerated across the plasma sheath. The sample is representative of the dose of positive ions implanted into the workpiece. The Faraday cup may include a multi-aperture cover for reducing the risk of discharge within the interior chamber of the Faraday cup. The Faraday cup may be configured to produce a lateral electric field within the interior chamber for suppressing escape of electrons, thereby improving measurement accuracy.

公开(公告)号：US06335536B1

公开(公告)日：2002-01-01

申请号：US09427872

申请日：1999-10-27

Applicant: Matthew J. Goeckner ,  Ziwei Fang

Inventor： Matthew J. Goeckner ,  Ziwei Fang

IPC: H01G37317

CPC classification number: H01J37/32412 ,  H01J37/32009

Abstract: A pulsed plasma doping system separates the plasma ignition function from the ion implantation function. An ignition voltage pulse is supplied to an ionizable gas and an implantation voltage pulse is applied to the target. The implantation voltage pulse can be generated from the ignition voltage pulse or can be generated separately from the ignition voltage pulse. Ions may be implanted in the target at an energy level that is below the Paschen curve for the system.

Abstract translation: 脉冲等离子体掺杂系统将等离子体点火功能与离子注入功能分离。 将点火电压脉冲提供给可电离气体，并将注入电压脉冲施加到靶。 注入电压脉冲可以从点火电压脉冲产生，也可以与点火电压脉冲分开产生。 离子可以在系统的Paschen曲线以下的能级被植入靶内。

公开(公告)号：US08592915B2

公开(公告)日：2013-11-26

申请号：US13012948

申请日：2011-01-25

Applicant: Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

Inventor： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

IPC: H01L29/76

CPC classification number: H01L21/76237 ,  H01L21/02321 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224

Abstract: The embodiments described provide methods and structures for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

Abstract translation: 所描述的实施例提供了用碳掺杂氧化物的方法和结构，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。 这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。 硬掩模层可用于保护下面的硅不被掺杂。 通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

公开(公告)号：US08450193B2

公开(公告)日：2013-05-28

申请号：US11770220

申请日：2007-06-28

Applicant: Jonathan Gerald England ,  Richard Stephen Muka ,  Edwin A. Arevalo ,  Ziwei Fang ,  Vikram Singh

Inventor： Jonathan Gerald England ,  Richard Stephen Muka ,  Edwin A. Arevalo ,  Ziwei Fang ,  Vikram Singh

IPC: H01L21/04

CPC classification number: H01L21/67115 ,  H01J37/20 ,  H01J2237/2001 ,  H01J2237/31701 ,  H01J2237/336 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67213 ,  H01L21/6831

Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise a platen to hold a wafer in a single-wafer process chamber during ion implantation, the platen including: a wafer clamping mechanism to secure the wafer onto the platen and to provide a predetermined thermal contact between the wafer and the platen, and one or more heating elements to pre-heat and maintain the platen in a predetermined temperature range above room temperature. The apparatus may also comprise a post-cooling station to cool down the wafer after ion implantation. The apparatus may further comprise a wafer handling assembly to load the wafer onto the pre-heated platen and to remove the wafer from the platen to the post-cooling station.

Abstract translation: 公开了用于温度控制离子注入的技术。 在一个特定的示例性实施例中，可以将技术实现为用于温度控制的离子注入的装置。 该设备可以包括在离子注入期间将晶片保持在单晶片处理室中的压板，压板包括：晶片夹紧机构，用于将晶片固定到压板上并在晶片和压板之间提供预定的热接触， 以及一个或多个加热元件以预热并将压板保持在高于室温的预定温度范围内。 该装置还可以包括后冷却站，以在离子注入之后冷却晶片。 该设备还可以包括晶片处理组件，以将晶片加载到预热台板上，并将晶片从压板移除到后冷却站。