公开(公告)号：US10749552B2

公开(公告)日：2020-08-18

申请号：US16140364

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Balwinder Singh ,  Milam Paraschou ,  Chad S. Gallun ,  Jeffrey Cooper ,  Dean E. Gonzales ,  Alushulla Jack Ambundo ,  Thomas H. Likens, III ,  Gerald R. Talbot

IPC: H04B1/04 ,  H03M1/80 ,  H01L27/02 ,  H04B1/16

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

公开(公告)号：US20200099406A1

公开(公告)日：2020-03-26

申请号：US16140364

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Balwinder Singh ,  Milam Paraschou ,  Chad S. Gallun ,  Jeffrey Cooper ,  Dean E. Gonzales ,  Alushulla Jack Ambundo ,  Thomas H. Likens, III ,  Gerald R. Talbot

IPC: H04B1/04 ,  H04B1/16 ,  H01L27/02 ,  H03M1/80

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

公开(公告)号：US10103837B2

公开(公告)日：2018-10-16

申请号：US15191322

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Stanley Ames Lackey, Jr. ,  Damon Tohidi ,  Gerald R. Talbot ,  Edoardo Prete

IPC: H04L1/00 ,  H04L7/00 ,  H04L12/70

Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.

公开(公告)号：US20250007516A1

公开(公告)日：2025-01-02

申请号：US18763572

申请日：2024-07-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar ,  Edoardo Prete ,  Gerald R. Talbot ,  Ethan Crain ,  Tracy J. Feist ,  Jeffrey Cooper

IPC: H03K19/0175 ,  H03F3/45

Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

公开(公告)号：US11960435B2

公开(公告)日：2024-04-16

申请号：US17692147

申请日：2022-03-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Pradeep Jayaraman ,  Dean Gonzales ,  Gerald R. Talbot ,  Ramon A. Mangaser ,  Michael J. Tresidder ,  Prasant Kumar Vallur ,  Srikanth Reddy Gruddanti ,  Krishna Reddy Mudimela Venkata ,  David H. McIntyre

IPC: G06F13/42 ,  H01L25/065

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H01L25/0652

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

公开(公告)号：US11805026B2

公开(公告)日：2023-10-31

申请号：US16993678

申请日：2020-08-14

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Stanley Ames Lackey, Jr. ,  Damon Tohidi ,  Gerald R. Talbot ,  Edoardo Prete

IPC: H04L41/147 ,  H04L43/50 ,  H04L43/0852 ,  H04L7/10 ,  H04L43/0823 ,  H04L25/14 ,  H04L7/06 ,  H04L7/00 ,  H04L7/04

CPC classification number: H04L41/147 ,  H04L7/06 ,  H04L7/10 ,  H04L25/14 ,  H04L43/0823 ,  H04L43/0852 ,  H04L43/50 ,  H04L7/0041 ,  H04L7/043

Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.

公开(公告)号：US20230342325A1

公开(公告)日：2023-10-26

申请号：US18216908

申请日：2023-06-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

公开(公告)号：US11693813B2

公开(公告)日：2023-07-04

申请号：US16427020

申请日：2019-05-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

公开(公告)号：US20220035765A1

公开(公告)日：2022-02-03

申请号：US17503959

申请日：2021-10-18

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Gerald R. Talbot

IPC: G06F13/42 ,  G06F13/12 ,  G06F13/40

Abstract: An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.

公开(公告)号：US11151075B2

公开(公告)日：2021-10-19

申请号：US16221181

申请日：2018-12-14

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Gerald R. Talbot

IPC: G06F13/42 ,  G06F13/12 ,  G06F13/40

Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.