公开(公告)号：US09465754B2

公开(公告)日：2016-10-11

申请号：US13930088

申请日：2013-06-28

Applicant: Analog Devices, Inc.

Inventor： Alexander Leonard ,  Shipra Bhal ,  Christopher Mayer

IPC: G06F13/16

CPC classification number: G06F13/1642 ,  G06F13/1673

Abstract: A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared set of registers. The monitor may monitor the plurality of commands in the queue to determine whether a period of time needs to be reserved for selected commands from one of the plurality of buses. The controller, if the period of time needs to be reserved, based on the period of time determined by the monitor, may disable acceptance of commands from buses other than the one of the plurality of buses, may execute the selected commands for the one of the plurality of buses, and may allow more than one of the plurality of buses access to results of the selected commands.

Abstract translation: 电路可以包括队列，监视器和控制器。 队列可以从多个总线接收并存储多个命令以访问共享的一组寄存器。 监视器可以监视队列中的多个命令，以确定是否需要为多个总线中的一个总线的选定命令保留一段时间。 控制器，如果需要保留的时间段，基于由监视器确定的时间段，可以禁止从除了多个总线之一的总线以外的总线接收命令，可以执行所选择的命令 多个总线，并且可以允许多个总线中的多于一个访问所选择的命令的结果。

公开(公告)号：US11907160B2

公开(公告)日：2024-02-20

申请号：US17817811

申请日：2022-08-05

Applicant: Analog Devices, Inc.

Inventor： Manish J. Manglani ,  Shipra Bhal ,  Christopher Mayer

IPC: G06F9/30 ,  G06F15/82 ,  G06F13/24 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F15/82 ,  G06F9/30123 ,  G06F9/3877 ,  G06F13/24 ,  G06F15/80

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

公开(公告)号：US11201600B1

公开(公告)日：2021-12-14

申请号：US16948887

申请日：2020-10-05

Applicant: Analog Devices, Inc.

Inventor： Christoph M. Steinbrecher ,  Ekrem Oran ,  Xizhen Xu ,  Christopher Mayer

IPC: H03H7/12

Abstract: Apparatus and methods for control and calibration of tunable filters are provided. In certain embodiments, a tunable filter includes at least one controllable component (for instance, a controllable inductor or a controllable capacitor) having a value that changes or adjusts a center frequency of the tunable filter. For example, the controllable component can correspond to a controllable inductor or a controllable capacitor of an inductor-capacitor (LC) resonator of the tunable filter. The tunable filter further includes a control circuit implemented with an approximation function for estimating a value of the controllable component for achieving a desired center frequency indicated by a frequency control signal.

公开(公告)号：US20200327095A1

公开(公告)日：2020-10-15

申请号：US16913251

申请日：2020-06-26

Applicant: Analog Devices, Inc.

Inventor： Manish J. Manglani ,  Shipra Bhal ,  Christopher Mayer

IPC: G06F15/82 ,  G06F13/24 ,  G06F9/30

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

公开(公告)号：US09979408B2

公开(公告)日：2018-05-22

申请号：US15147408

申请日：2016-05-05

Applicant: ANALOG DEVICES, INC.

Inventor： Christopher Mayer ,  David J. McLaurin ,  Christopher W. Angell ,  Sudhir Desai ,  Steven R. Bal

IPC: H03L7/091 ,  H03L7/093 ,  H04B7/0413 ,  H03L7/087 ,  H03L7/23 ,  H03L7/197 ,  H03L7/089 ,  H04L7/033

CPC classification number: H03L7/1976 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/093 ,  H03L7/23 ,  H03L7/235 ,  H04B7/0413 ,  H04L7/0331

Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

公开(公告)号：US09614557B1

公开(公告)日：2017-04-04

申请号：US14954857

申请日：2015-11-30

Applicant: Analog Devices, Inc.

Inventor： Christopher Mayer ,  David J. McLaurin ,  Chris Angell

IPC: H04B1/38 ,  H04L5/16 ,  H04B1/04 ,  H04L1/00 ,  H04B17/13

CPC classification number: H04B1/0475 ,  H04B1/40 ,  H04B17/13 ,  H04B2001/0425 ,  H04L1/0042

Abstract: A method and apparatus for phase adjustment of a RF transceiver is disclosed. Based on a first local oscillator signal and a second local oscillator signal, a beat signal that indicates the frequency and phase relationship between the first and second local oscillator signals can be generated. Using the beat signal, changing phase relationship between the first and second local oscillator signals can be cumulatively taken account for using phase averaging to allow quick restoration to observation of a previously observed channel.

公开(公告)号：US20140105264A1

公开(公告)日：2014-04-17

申请号：US13650707

申请日：2012-10-12

Applicant: ANALOG DEVICES, INC.

Inventor： David J. McLaurin ,  Christopher Mayer

IPC: H04B17/00

CPC classification number: H04B17/11

Abstract: A system and method provide for calibrating the frequency response of an electronic filter. The system and method include a radio transmitter with both in-phase and quadrature baseband paths. Each baseband path includes a numerically controlled oscillator (“NCO”), a digital signal path, a digital-to-analog converter (“DAC”), and an analog filter. A low frequency tone is applied from the NCO from one of the baseband path, while a high frequency tone is applied from the NCO in the other baseband path. An analog peak detector at output determines which analog filter has the largest amplitude at the output. The peak detector offset between the two analog filters is offset by stimulating the in-phase and quadrature baseband paths with the respective NCOs to find an amplitude difference between the output signals from the NCOs that makes the output of the analog filters the same. Calibration is then performed on the corner frequency and filter peaking through respective stimulation of the in-phase and quadrature baseband paths. The system and method is advantageous as it allows for very accurate calibration of both the filter corner frequency and peaking during a standard transmission operating mode with little additional hardware required.

Abstract translation: 一种用于校准电子滤波器的频率响应的系统和方法。 该系统和方法包括具有同相和正交基带路径的无线电发射机。 每个基带路径包括数控振荡器（“NCO”），数字信号路径，数模转换器（“DAC”）和模拟滤波器。 来自基带路径之一的NCO施加低频音调，而在另一个基带路径中从NCO施加高频音调。 输出端的模拟峰值检测器决定了哪个模拟滤波器在输出端具有最大幅度。 两个模拟滤波器之间的峰值检测器偏移通过用相应的NCO刺激同相和正交基带路径来偏移，以在来自NCO的输出信号之间找到使模拟滤波器的输出相同的振幅差。 然后在角频率上进行校准，并通过相位和正交基带路径的相应刺激来过滤峰值。 该系统和方法是有利的，因为它允许在标准传输操作模式期间非常精确地校准滤波器转角频率和峰值，同时需要少量额外的硬件。