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    Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges
    21.
    发明授权
    Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges 有权

    公开(公告)号：US11303268B2

    公开(公告)日：2022-04-12

    申请号：US17173055

    申请日：2021-02-10

    Applicant: Apple Inc.

    Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

    IPC: H03K3/037 ,  H03K19/096 ,  H03K3/64

    Abstract: A system and method for efficiently storing and driving data between pipeline stages. In various embodiments, a flip-flop circuit includes a bypass circuit, which is a tri-state inverter, and the bypass circuit receives a clock signal and a version of a data signal. When the clock signal received by the flip-flop circuit is asserted, the output of the bypass circuit is sent as the output of the flip-flop circuit. In one example, the version of the data signal received by the bypass circuit is the data signal. In another example, the version of the data signal received by the bypass circuit is the output of a master latch. Although the output of the master latch is pre-charged, when the clock is asserted, each of a late arriving rising and falling data transition are included in the critical path of the flip-flop circuit.

    Hybrid power switch
    22.
    发明授权
    Hybrid power switch 有权

    公开(公告)号：US10732693B2

    公开(公告)日：2020-08-04

    申请号：US16379451

    申请日：2019-04-09

    Applicant: Apple Inc.

    Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

    IPC: G05F1/46 ,  G06F1/3206 ,  H03K17/62 ,  H03K17/22 ,  G06F1/3287 ,  G06F1/3296 ,  G06F30/39

    Abstract: A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.

    Power grid segmentation for memory arrays
    24.
    发明授权
    Power grid segmentation for memory arrays 有权
    存储阵列的电网分割

    公开(公告)号：US09529533B1

    公开(公告)日：2016-12-27

    申请号：US15177596

    申请日：2016-06-09

    Applicant: Apple Inc.

    Inventor： Michael A. Dreesen ,  Naveen Javarappa ,  Ajay Kumar Bhatia ,  Greg M. Hess

    IPC: G11C5/14 ,  G06F3/06 ,  G06F1/32 ,  G06F1/26 ,  G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/418 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/417 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/172

    Abstract: An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.

    Abstract translation: 公开了一种用于修改存储器阵列电源的电压电平的装置。 第一列可以包括耦合到第一本地电源信号的第一多个数据存储单元，并且第二列可以包括耦合到第二本地电源信号的第二多个数据存储单元。 第一开关可以被配置为根据第一选择信号的值将第一本地电源信号选择性地耦合到第一电源信号或第二电源信号，并且第二开关可被配置为选择性地将第二本地电源信号 根据第二选择信号的值将电源信号提供给第一电源信号或第二电源信号。

    SRAM regulating retention scheme with discrete switch control and instant reference voltage generation
    25.
    发明授权
    SRAM regulating retention scheme with discrete switch control and instant reference voltage generation 有权
    具有分立开关控制和即时参考电压产生的SRAM调节保持方案

    公开(公告)号：US09411406B2

    公开(公告)日：2016-08-09

    申请号：US13921475

    申请日：2013-06-19

    Applicant: Apple Inc.

    Inventor： Bo Tang ,  Ajay Kumar Bhatia

    IPC: G06F1/26 ,  G06F1/32 ,  G05F1/46

    CPC classification number: G06F1/3275 ,  G05F1/468 ,  G06F1/26 ,  G06F1/32

    Abstract: A system including control logic, a voltage reference, a sense amplifier, and a voltage supply circuit is presented. The sense amplifier may be configured to detect a current state of the voltage supply circuit output compared to the reference voltage. The voltage supply circuit may be configured to capture and preserve the current state to be used as a previous state. The voltage regulator may be configured to compare the current state to one or more previous states and adjust the voltage regulator output based on the comparison. Control logic may be configured to enable the voltage reference output in response to a signal. Control logic may be configured to enable the sense amplifier at a time after the voltage reference is stable. Control logic may be configured to disable the voltage reference output in response to the sense amplifier generating an output.

    Abstract translation: 提出了一种包括控制逻辑，电压基准，读出放大器和电压供应电路的系统。 读出放大器可被配置为检测与参考电压相比的电压供应电路输出的当前状态。 电压供给电路可以被配置为捕获并保持用作先前状态的当前状态。 电压调节器可以被配置为将当前状态与一个或多个先前状态进行比较，并且基于比较来调节稳压器输出。 控制逻辑可以被配置为响应于信号启用电压参考输出。 控制逻辑可以被配置为在电压参考稳定之后的时间使能读出放大器。 控制逻辑可以被配置为响应于感测放大器产生输出来禁用电压参考输出。

    Low power double pumped multi-port register file architecture
    26.
    发明授权
    Low power double pumped multi-port register file architecture 有权
    低功率双泵浦多端口寄存器文件架构

    公开(公告)号：US09361959B2

    公开(公告)日：2016-06-07

    申请号：US14467376

    申请日：2014-08-25

    Applicant: Apple Inc.

    Inventor： Ajay Kumar Bhatia ,  Aravind Kandala

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/419 ,  G11C2207/2254 ,  G11C2207/229

    Abstract: Embodiments that may allow for selectively tuning a delay of individual write paths within a memory are disclosed. The memory may comprise a memory array, a first data latch, a second data latch, and circuitry. The first and second data latches may be configured to each sample a respective data value, responsive to detecting a first edge of a first clock signal. The circuitry may be configured to detect the first edge of the first clock signal, and select an output of the first data latch responsive to detecting the first edge of the first clock signal. The circuitry may detect a subsequent opposite edge of the first clock signal, and select an output of the second data latch responsive to sampling the opposite edge of the first clock signal.

    Abstract translation: 公开了可以允许选择性地调整存储器内的各个写入路径的延迟的实施例。 存储器可以包括存储器阵列，第一数据锁存器，第二数据锁存器和电路。 响应于检测到第一时钟信号的第一边缘，第一和第二数据锁存器可以被配置为对各自的数据值进行采样。 电路可以被配置为检测第一时钟信号的第一边缘，并且响应于检测到第一时钟信号的第一边缘而选择第一数据锁存器的输出。 电路可以检测第一时钟信号的后续相对边缘，并且响应于对第一时钟信号的相对边缘采样来选择第二数据锁存器的输出。

    VOLTAGE SAMPLING SCHEME WITH DYNAMICALLY ADJUSTABLE SAMPLE RATES
    28.
    发明申请
    VOLTAGE SAMPLING SCHEME WITH DYNAMICALLY ADJUSTABLE SAMPLE RATES 有权
    电压采样方案采用动态可调取样品速率

    公开(公告)号：US20160043705A1

    公开(公告)日：2016-02-11

    申请号：US14455195

    申请日：2014-08-08

    Applicant: Apple Inc.

    Inventor： Bo Tang ,  Ajay Kumar Bhatia

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  H03K5/24 ,  H03K5/249 ,  H03K19/0013

    Abstract: A apparatus including a clock source and a comparison circuit is presented. The clock source may be configured to generate a clock signal. The comparison circuit may be configured select a first frequency of the clock signal and to receive a plurality of voltage signal inputs for comparison. The comparison circuit may be further configured to compare a voltage level of a first voltage signal input of the plurality of voltage signal inputs to a voltage level of a second voltage signal input of the plurality of voltage signal inputs responsive to an active edge of the clock signal. The comparison circuit may also be configured to determine a comparison value corresponding to the comparison of the voltage levels and to select a second frequency of the clock signal dependent upon the comparison value, in which the second frequency is different than the first frequency.

    Abstract translation: 提出了一种包括时钟源和比较电路的装置。 时钟源可以被配置为产生时钟信号。 比较电路可以被配置为选择时钟信号的第一频率并且接收多个电压信号输入用于比较。 比较电路还可以被配置为将响应于时钟的有效边沿将多个电压信号输入的第一电压信号输入的电压电平与多个电压信号输入的第二电压信号输入的电压电平进行比较 信号。 比较电路还可以被配置为确定对应于电压电平的比较的比较值，并且根据比较值选择时钟信号的第二频率，其中第二频率不同于第一频率。

    BALANCED LEVEL SHIFTER WITH WIDE OPERATION RANGE
    29.
    发明申请
    BALANCED LEVEL SHIFTER WITH WIDE OPERATION RANGE 有权
    平衡水平移动与宽操作范围

    公开(公告)号：US20140232445A1

    公开(公告)日：2014-08-21

    申请号：US13769406

    申请日：2013-02-18

    Applicant: APPLE INC.

    Inventor： Bo Tang ,  Huaimin Li ,  Ajay Kumar Bhatia

    IPC: H03K5/003

    CPC classification number: H03K5/003 ,  H03K3/356104

    Abstract: Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals.

    Abstract translation: 公开了一种装置的实施例，其可以允许将信号从一个功率域转换到另一个功率域，并且在宽的工作范围内具有良好平衡的上升和下降时间。 该装置可以包括输入缓冲器，电压移位电路和输出电路以及输出驱动器。 输入缓冲器可以被配置为在第一电压电平下产生缓冲版本和外部信号的延迟反相版本。 电压移位电路可以被配置为根据输入缓冲器的输出信号产生处于第二电压电平的两个内部信号。 输出电路可以被配置为根据电压移位电路的输出信号产生处于第二电压电平的两个输出驱动器信号。 输出驱动器电路可以被配置为根据两个输出驱动器信号产生处于第二电压电平的输出信号。

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