公开(公告)号：US20180183456A1

公开(公告)日：2018-06-28

申请号：US15849227

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link ,  Jianping Wen

IPC: H03M1/46 ,  H03M1/44

CPC classification number: H03M1/462 ,  H03M1/0626 ,  H03M1/08 ,  H03M1/442 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

公开(公告)号：US08643525B1

公开(公告)日：2014-02-04

申请号：US13733301

申请日：2013-01-03

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Amit Kumar ,  Garry N. Link ,  Wai Laing Lee

IPC: H03M1/66

CPC classification number: H03M1/067 ,  H03M1/74 ,  H03M3/502

Abstract: A system and method dynamically selects digital-to-analog (DAC) circuit elements to provide a True differential-output delta-sigma (ΔΣ) DAC. The sign and magnitude of a received N-bit input code is determined. If the input code comprises a positive value, m+r circuit elements are selected from a plurality of circuit elements by a positive element selector, in which comprises a number of rotational elements, and r circuit elements are selected by a negative element selector. Each selected circuit element comprises a circuit element that was not selected for an immediately preceding received input code and has a corresponding minimum usage count value. If the input digital code comprises a negative value, m+r circuit elements are selected by the negative element selector, and r circuit elements are selected by the positive element selector. The circuit elements are capable of being configured as positive or negative circuit elements.

Abstract translation: 一种系统和方法动态地选择数模（DAC）电路元件，以提供真差分输出Δ-Σ（DeltaSigma）DAC。 确定接收到的N位输入代码的符号和大小。 如果输入代码包括正值，则通过正元件选择器从多个电路元件中选择m + r个电路元件，其中包括多个旋转元件，并且r个电路元件由负元件选择器选择。 每个所选择的电路元件包括未被选择用于紧接在前的接收输入代码并且具有对应的最小使用计数值的电路元件。 如果输入数字代码包含负值，则由负选择器选择m + r个电路元件，并且通过正元件选择器选择r个电路元件。 电路元件能够被配置为正或负电路元件。

公开(公告)号：US10574254B2

公开(公告)日：2020-02-25

申请号：US16173398

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/44 ,  H03M1/10 ,  H03M1/18

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

公开(公告)号：US20190173486A1

公开(公告)日：2019-06-06

申请号：US16174088

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US20190173483A1

公开(公告)日：2019-06-06

申请号：US16174071

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link ,  Jianping Wen

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/08 ,  H03M1/44

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

公开(公告)号：US10263629B2

公开(公告)日：2019-04-16

申请号：US15991871

申请日：2018-05-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/36 ,  H03M1/10 ,  H03M1/46

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US09831887B2

公开(公告)日：2017-11-28

申请号：US15391573

申请日：2016-12-27

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

IPC: H03M1/10 ,  H03M1/38

CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

公开(公告)号：US20170250703A1

公开(公告)日：2017-08-31

申请号：US15490759

申请日：2017-04-18

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

CPC classification number: H03M3/496 ,  H03M3/376 ,  H03M3/438

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US09741333B2

公开(公告)日：2017-08-22

申请号：US14148533

申请日：2014-01-06

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Wai Lang Lee ,  Jianping Wen

IPC: G10K11/16 ,  G10K11/178

CPC classification number: G10K11/178 ,  G10K11/17853 ,  G10K11/17873 ,  G10K11/17875 ,  G10K11/17879 ,  G10K2210/3016 ,  G10K2210/3026 ,  G10K2210/3027 ,  G10K2210/3028 ,  H04R2460/01

Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.

公开(公告)号：US20170126240A1

公开(公告)日：2017-05-04

申请号：US15391573

申请日：2016-12-27

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

IPC: H03M1/10 ,  H03M1/38

CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.