中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.025 seconds)

    METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS
    21.
    发明申请
    METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS 审中-公开
    通过插入界面原子单体与第IV组半导体的金属接触

    公开(公告)号：US20160163813A1

    公开(公告)日：2016-06-09

    申请号：US15043035

    申请日：2016-02-12

    Applicant: Acorn Technologies, Inc.

    Inventor： Walter A. Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

    IPC: H01L29/47

    CPC classification number: H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

    Abstract translation: 通过在金属和半导体之间的界面处插入V族或III族原子的单层或者插入由每个单层的单层构成的双层来降低金属 - 半导体（IV族）结的特定接触电阻的技术， 或插入多个这样的双层。 所得到的低比电阻金属组IV半导体结可用作包括电子器件（例如，晶体管，二极管等）和光电器件（例如，激光器，太阳能电池，光电检测器等）的半导体器件中的低电阻电极， 和/或作为场效应晶体管（FET）中的金属源极和/或漏极区域（或其一部分）。 III族和V族原子的单层主要是在IV族半导体的表面上形成的化学键合到IV族半导体的表面原子上的原子的有序层。

    SOI wafers and devices with buried stressor
    22.
    发明授权
    SOI wafers and devices with buried stressor 有权

    公开(公告)号：US10833194B2

    公开(公告)日：2020-11-10

    申请号：US16283578

    申请日：2019-02-22

    Applicant: Acorn Technologies, Inc.

    Inventor： Paul A. Clifton ,  Andreas Goebel

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02

    Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

    MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR
    25.
    发明申请
    MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR 审中-公开

    公开(公告)号：US20190067439A1

    公开(公告)日：2019-02-28

    申请号：US16175637

    申请日：2018-10-30

    Applicant: Acorn Technologies, Inc.

    Inventor： Paul A. Clifton ,  Andreas Goebel

    IPC: H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L29/36 ,  H01L29/51 ,  H01L21/28

    CPC classification number: H01L29/4966 ,  H01L21/28017 ,  H01L29/0895 ,  H01L29/36 ,  H01L29/517 ,  H01L29/66643

    Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10−5-10−7 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm−3 and less than approximately 10−8 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm−3.

    MIS contact structure with metal oxide conductor
    27.
    发明授权
    MIS contact structure with metal oxide conductor 有权

    公开(公告)号：US09620611B1

    公开(公告)日：2017-04-11

    申请号：US15186378

    申请日：2016-06-17

    Applicant: Acorn Technologies, Inc.

    Inventor： Paul A. Clifton ,  Andreas Goebel

    IPC: H01L29/36 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

    CPC classification number: H01L29/4966 ,  H01L21/28017 ,  H01L29/0895 ,  H01L29/36 ,  H01L29/517 ,  H01L29/66643

    Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10−5-10−7 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm−3 and less than approximately 10−8 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm−3.

    METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS
    29.
    发明申请
    METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS 有权
    通过插入界面原子单体与第IV组半导体的金属接触

    公开(公告)号：US20140327142A1

    公开(公告)日：2014-11-06

    申请号：US14360473

    申请日：2012-10-18

    Applicant: ACORN TECHNOLOGIES, INC.

    Inventor： Walter A Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

    IPC: H01L29/45 ,  H01L21/283

    CPC classification number: H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

    Abstract translation: 通过在金属和半导体之间的界面处插入V族或III族原子的单层或者插入由每个单层单层制成的双层来降低金属 - 半导体（IV族）结的特定接触电阻的技术， 或插入多个这样的双层。 所得到的低比电阻金属组IV半导体结可用作包括电子器件（例如，晶体管，二极管等）和光电器件（例如，激光器，太阳能电池，光电检测器等）的半导体器件中的低电阻电极， 和/或作为场效应晶体管（FET）中的金属源极和/或漏极区域（或其一部分）。 III族和V族原子的单层主要是在IV族半导体的表面上形成的化学键合到IV族半导体的表面原子上的原子的有序层。

Patent Agency Ranking