公开(公告)号：US20070298524A1

公开(公告)日：2007-12-27

申请号：US11425913

申请日：2006-06-22

Applicant: DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

Inventor： DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/34 ,  G03F7/70658 ,  H01L22/12

Abstract: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Abstract translation: 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。

公开(公告)号：US06593623B1

公开(公告)日：2003-07-15

申请号：US09400524

申请日：1999-09-20

Applicant: Akif Sultan

Inventor： Akif Sultan

IPC: H01L2994

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/6656 ,  H01L29/7836

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).

Abstract translation: 一种降低轻掺杂漏极晶体管（50）的有效沟道长度的方法包括以下步骤：在半导体衬底（56）上形成栅电极（52）和栅极氧化物（54），并注入漏区（58） ）具有亚非晶体大倾斜角植入物，从而在栅极氧化物（54）下方的位置处提供间隙（62）。 该方法还包括在衬底（56）的漏区（58）中形成轻掺杂漏极延伸区（66），并在漏极区（58）中形成漏极（70）并形成源延伸区（67） 以及在所述基底（56）的源极区（60）中的源极（72）。 最后，该方法包括热处理衬底（56），其中间隙（62）增强栅极氧化物（54）下方的横向扩散（84），而基本上不影响延伸区域（66,67）的垂直扩散（86） ），从而降低有效沟道长度，而不会增加漏极（70）和漏极延伸区域（66）或源极（72）和源极延伸区域（67）的结深度。

公开(公告)号：US08497179B2

公开(公告)日：2013-07-30

申请号：US12684697

申请日：2010-01-08

Applicant: Akif Sultan

Inventor： Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of fabricating p-type metal oxide semiconductor (PMOS) transistor devices on a common substrate is presented. The method provides a first portion of semiconductor material and a second portion of semiconductor material on the common substrate. The first portion of semiconductor material and the second portion of semiconductor material are insulated from each other. The method continues by creating first PMOS transistor devices using the first portion of semiconductor material. The first PMOS transistor devices include stressor regions that impart compressive stress to channel regions of the first PMOS transistor devices. The method also creates second PMOS transistor devices using the second portion of semiconductor material. The second PMOS transistor devices do not include channel stressor regions.

Abstract translation: 提出了在公共衬底上制造p型金属氧化物半导体（PMOS）晶体管器件的方法。 该方法提供半导体材料的第一部分和半导体材料的第二部分在公共基底上。 半导体材料的第一部分和半导体材料的第二部分彼此绝缘。 该方法通过使用半导体材料的第一部分创建第一PMOS晶体管器件来继续。 第一PMOS晶体管器件包括对第一PMOS晶体管器件的沟道区赋予压应力的应力源区域。 该方法还使用半导体材料的第二部分创建第二PMOS晶体管器件。 第二PMOS晶体管器件不包括沟道应力区域。

公开(公告)号：US08377781B2

公开(公告)日：2013-02-19

申请号：US13230083

申请日：2011-09-12

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US07761838B2

公开(公告)日：2010-07-20

申请号：US11861492

申请日：2007-09-26

Applicant: Zhonghai Shi ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

Inventor： Zhonghai Shi ,  Mark Michael ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

IPC: G06F17/50 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract translation: 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US07638837B2

公开(公告)日：2009-12-29

申请号：US11861051

申请日：2007-09-25

Applicant: Akif Sultan ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu

Inventor： Akif Sultan ,  Mark Michael ,  David Wu

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

Abstract translation: 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。

公开(公告)号：US07582493B2

公开(公告)日：2009-09-01

申请号：US11538872

申请日：2006-10-05

Applicant: Akif Sultan ,  James F. Buller ,  David Donggang Wu

Inventor： Akif Sultan ,  James F. Buller ,  David Donggang Wu

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/14

Abstract: A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.

Abstract translation: 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用该测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

公开(公告)号：US06979635B1

公开(公告)日：2005-12-27

申请号：US10759171

申请日：2004-01-20

Applicant: Akif Sultan ,  Qi Xiang ,  Bin Yu

Inventor： Akif Sultan ,  Qi Xiang ,  Bin Yu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

Abstract translation: 通过图案化多晶硅栅极前体，通过选择性地氧化其上表面和侧表面，然后去除氧化表面而减小其宽度和高度来形成超窄和多晶硅栅电极。 实施例包括用其下面的氧化物层图案化多晶硅栅极前体，离子注入以形成深源极/漏极区域，在多晶硅栅极前体的每一侧的衬底表面上形成氮化物层，热氧化多晶硅的上表面和侧表面 从而消耗硅，然后去除氧化的上表面和侧表面，留下具有减小的宽度和降低的高度的多晶硅栅电极。 随后的处理包括形成浅源极/漏极延伸部分，在多晶硅栅电极上形成电介质侧壁间隔物，然后在多晶硅栅极电极的上表面上以及在源极/漏极区域上形成金属硅化物层。

公开(公告)号：US06642536B1

公开(公告)日：2003-11-04

申请号：US10015802

申请日：2001-12-17

Applicant: Qi Xiang ,  Akif Sultan

Inventor： Qi Xiang ,  Akif Sultan

IPC: H01L2906

CPC classification number: H01L21/76264 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78639 ,  H01L29/78654

Abstract: Silicon on insulator technology and strained silicon technology provide semiconductor devices with high performance capabilities. Shallow trench isolation technology provides smaller devices with increased reliability. Bulk silicon technology provides devices requiring deep ion implant capabilities and/or a high degree of thermal management. A semiconductor device including silicon on insulator regions, strained silicon layer, shallow trench isolation structures, and bulk silicon regions is provided on a single semiconductor substrate.

Abstract translation: 硅绝缘体技术和应变硅技术为半导体器件提供了高性能的能力。 浅沟槽隔离技术为更小的器件提供了更高的可靠性。 散装硅技术提供了需要深度离子注入能力和/或高度热管理的器件。 包括硅绝缘体区域，应变硅层，浅沟槽隔离结构和体硅区域的半导体器件设置在单个半导体衬底上。

公开(公告)号：US06475885B1

公开(公告)日：2002-11-05

申请号：US09896490

申请日：2001-06-29

Applicant: Akif Sultan

Inventor： Akif Sultan

IPC: H01L21425

CPC classification number: H01L29/66772 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/78609

Abstract: Various methods of fabricating a source/drain structure are provided. In one aspect, a method of processing a semiconductor workpiece is provided that includes implanting a neutral ion species into the substrate at a sub-amorphizing dosage to provide a plurality of interstitials and forming a source/drain region in the substrate by implanting impurities of a first conductivity type proximate the plurality of interstitials. The plurality of interstitials retards diffusion of the impurities. Impurity diffusion is retarded, resulting in better activation and a more abrupt impurity profile.

Abstract translation: 提供了制造源极/漏极结构的各种方法。 在一个方面，提供了一种处理半导体工件的方法，其包括以亚非晶化剂量将中性离子物质注入衬底中以提供多个间隙，并通过植入杂质形成衬底中的源极/漏极区域 靠近多个间隙的第一导电类型。 多个间隙延迟杂质的扩散。 杂质扩散延迟，导致更好的活化和更突变的杂质分布。