公开(公告)号：US11967650B2

公开(公告)日：2024-04-23

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US10943976B2

公开(公告)日：2021-03-09

申请号：US16537725

申请日：2019-08-12

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Washington Lamar

IPC: H01L29/08 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8234

Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

公开(公告)号：US10256225B2

公开(公告)日：2019-04-09

申请号：US15601141

申请日：2017-05-22

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar

IPC: H01L27/02 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/87 ,  H01L29/417 ,  H01L29/78

Abstract: A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.

公开(公告)号：US10145904B2

公开(公告)日：2018-12-04

申请号：US15245689

申请日：2016-08-24

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  William P. Taylor

IPC: H01L27/02 ,  H01L43/02 ,  H01L43/12 ,  G01R33/00 ,  H01L23/60

Abstract: An apparatus includes a package, a plurality of external connections extending outside the package, and a first die having a first electrical contact coupled to a first connection of the plurality of external connections. The apparatus also includes a second die having a second electrical contact coupled to a second connection of the plurality of external connections. A conductor is electrically coupled between the first contact and the second contact to allow electrostatic discharge current to flow between the first die to the second die.

公开(公告)号：US10056364B1

公开(公告)日：2018-08-21

申请号：US15481882

申请日：2017-04-07

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Richard B. Cooper ,  Chung C. Kuo

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/40 ,  H01L29/866 ,  H01L29/739

CPC classification number: H01L27/0255 ,  H01L29/402 ,  H01L29/866

Abstract: An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped region of the substrate having an n doping type, wherein an interface between the first and second doped regions forms a p-n junction; and a circuit element placed in spaced relation to the p-n junction, the circuit element configured to produce an electric field that interacts with the p-n junction to change a reverse breakdown voltage of the p-n junction. Applicants for the electrical device include ESD protection circuits.

公开(公告)号：US20180190599A1

公开(公告)日：2018-07-05

申请号：US15907445

申请日：2018-02-28

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov

IPC: H01L23/60 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49589 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/19105 ,  H01L2924/00014

Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

公开(公告)号：US20180083442A1

公开(公告)日：2018-03-22

申请号：US15272784

申请日：2016-09-22

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov

IPC: H02H9/04

CPC classification number: H02H9/041

Abstract: An apparatus includes a first terminal, a second terminal, and a conduction path circuit coupled between the first and second terminals. The conduction path circuit includes an input terminal to receive an enable signal which, when activated, allows the conduction path circuit to conduct electrical current between the first and second terminal. A control circuit coupled to the input terminal of the conduction path circuit is configured to selectively activate the enable signal.

公开(公告)号：US20160282893A1

公开(公告)日：2016-09-29

申请号：US15161529

申请日：2016-05-23

Applicant: Allegro Microsystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G05F3/02 ,  H01L43/02

CPC classification number: G05F3/02 ,  H01L27/0259 ,  H01L27/0266 ,  H01L43/02 ,  H03K19/00361

Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

Abstract translation: 电子电路包括具有耦合到半导体衬底的第一掺杂型和参考端的半导体衬底。 在半导体衬底中形成具有第二掺杂类型的桶区。 具有第一掺杂类型的阱区形成在桶区内。 包括晶体管的驱动电路形成在阱区内并具有输出端。 控制电路耦合到驱动电路以控制驱动器电路。 第二晶体管在阱区内并且串联耦合在驱动器电路和输出端之间，第二晶体管具有耦合到驱动电路的第一端子和耦合到输出端的第二端子。 偏置电路耦合到第二晶体管的栅极端子并且被配置为将晶体管偏置为导通状态。