公开(公告)号：US10215698B2

公开(公告)日：2019-02-26

申请号：US14569235

申请日：2014-12-12

Applicant: Apple Inc.

Inventor： Chin San Han ,  Ueyn Block ,  Brian R. Land ,  Nevzat Akin Kestelli ,  Serhan Isikman ,  Albert Wang ,  Justin Shi

IPC: A61B6/00 ,  G01N21/47 ,  G01N21/55 ,  A61B5/00 ,  A61B5/024

Abstract: A photoplethysmographic (PPG) device is disclosed. The PPG device can include one or more light emitters and one or more light sensors to generate the multiple light paths for measuring a PPG signal and perfusion indices of a user. The multiple light paths between each pair of light emitters and light detectors can include different separation distances to generate both an accurate PPG signal and a perfusion index value to accommodate a variety of users and usage conditions. In some examples, the multiple light paths can include the same separation distances for noise cancellation due to artifacts resulting from, for example, tilt and/or pull of the device, a user's hair, a user's skin pigmentation, and/or motion. The PPG device can further include one or more lenses and/or reflectors to increase the signal strength and/or and to obscure the optical components and associated wiring from being visible to a user's eye.

公开(公告)号：US20180337003A1

公开(公告)日：2018-11-22

申请号：US15600329

申请日：2017-05-19

Applicant: Apple Inc.

Inventor： Ming Y. Tsai ,  Albert Wang ,  Curtis C. Mead ,  Tyler S. Bushnell ,  Paul A. Martinez

IPC: H01G4/35 ,  H01G4/12 ,  H01G4/005 ,  H01G4/30 ,  H01L41/047

CPC classification number: H01G4/35 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: Monolithic capacitor structures having a main capacitor and a vise capacitor are discussed. The vise capacitor provides to the monolithic capacitor structure reduced vibrations and/or acoustic noise due to piezoelectric effects. To that end, vise capacitor may cause piezoelectric deformations that compensate the deformations that are caused by the electrical signals in the main capacitor. Embodiments of these capacitor structures may have the main capacitor and the vise capacitor sharing portions of a rigid dielectric. Electrical circuitry that employs the vise capacitor to reduce noise and/or vibration in the monolithic capacitor structures is also described. Methods for fabrication of these capacitors are discussed as well.

公开(公告)号：US09971407B2

公开(公告)日：2018-05-15

申请号：US14870697

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Prashanth Holenarsipur ,  Albert Wang ,  Yuta Kuboyama

IPC: G06F3/01 ,  G06F3/0362

CPC classification number: G06F3/016 ,  G06F3/0362

Abstract: An electronic device is disclosed. In some examples, the electronic device comprises a mechanical input configured to rotate in a first direction about a rotation axis in response to a first input at the mechanical input. In some examples, the electronic device comprises a mechanical input sensor coupled to the mechanical input and configured to sense a rotation of the mechanical input about the rotation axis. In some examples, the electronic device comprises a mechanical input actuator coupled to the mechanical input and configured to rotate the mechanical input in a second direction about the rotation axis. In some examples, the mechanical input comprises a shared driving and sensing segment. In some examples, the mechanical input sensor is configured to sense the rotation of the mechanical input at the shared driving and sensing segment. In some examples, the mechanical input actuator is configured to generate magnetic fields for rotating the mechanical input at the shared driving and sensing segment. In some examples, the mechanical input is further configured to translate along the rotation axis in response to a second input. In some examples, the mechanical input actuator comprises at least one piezoelectric element configured to allow the mechanical input to translate along the rotation axis. In some examples, the mechanical input actuator comprises at least one piezoelectric element configured to rotate the mechanical input in the second direction about the rotation axis.

公开(公告)号：US20180092210A1

公开(公告)日：2018-03-29

申请号：US15274302

申请日：2016-09-23

Applicant: Apple Inc.

Inventor： Albert Wang ,  Paul A. Martinez

IPC: H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H05K3/30 ,  H05K3/28 ,  H05K3/36 ,  H05K3/34 ,  H05K3/40 ,  H05K3/00

CPC classification number: H05K1/145 ,  H05K1/0218 ,  H05K1/0278 ,  H05K1/0281 ,  H05K1/0298 ,  H05K1/181 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/284 ,  H05K3/303 ,  H05K3/341 ,  H05K3/361 ,  H05K3/4038 ,  H05K3/4046 ,  H05K3/4614 ,  H05K2201/042 ,  H05K2201/0707 ,  H05K2201/09118 ,  H05K2201/10522 ,  H05K2201/10734 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: Methods and devices related to the design and fabrication of molded cores for printed circuit board assemblies and system-on-package (SIP) devices are discussed. The discussed printed circuit board assemblies may have multiple electrical components embedded in a molded core matrix and forming electrical connections with one or more printed circuit boards attached to the molded core matrix. Methods for sourcing of electrical components and production of the molded cores and printed circuit board assemblies are also discussed. The methods and devices may increase a volumetric density of electrical components in printed circuit board assemblies and provide improved mechanical properties to the electrical circuit device.

公开(公告)号：US20170208690A1

公开(公告)日：2017-07-20

申请号：US15275369

申请日：2016-09-24

Applicant: Apple Inc.

Inventor： Paul A. Martinez ,  Curtis C. Mead ,  Scott D. Morrison ,  Giancarlo F. De La Cruz ,  Lin Chen ,  Albert Wang ,  Brad W. Simeral ,  Vu Vo ,  Wyeman Chen

IPC: H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/228 ,  H01G4/38 ,  H01G4/005 ,  H01G2/06 ,  H05K3/30 ,  H01G4/40

Abstract: Systems and methods described in this disclosure are related to fabrication and utilization of two-terminal electrical components that may have terminations with reduced width. Components, such as the ones described herein may be used to increase the density of components in electrical devices, as they may reduce a separation distance between devices that lead to solder bridging. Methods for fabrication are also described, including the use of ceramic layers that may provide reduction in parasitic capacitance and/or inductances.